Time-Interleaved ADC Timing and Bandwidth Matching
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Solution Overview
Problem
Time-interleaving analog-to-digital converters (ADCs) face issues with mismatch in bandwidth, sampling time, gain, and offset, leading to intermodulation distortion, which degrades the spurious-free dynamic range (SFDR) and signal-to-noise and distortion ratio (SNDR) due to differences in the characteristics of individual ADCs.
Innovation Solution
The implementation of special circuitry and calibration methods to measure and adjust bandwidth, sampling time, gain, and offset mismatches between ADCs, using digital correction coefficients stored in memory elements like OTP memory, to equalize these parameters and minimize intermodulation distortion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple lower sample rate ADCs are used in time-interleaved configuration, then the overall sample rate is increased, but mismatch in bandwidth, sampling time, gain, and offset degrades dynamic performance
Solution Approach 1:
The high sample rate ADC is segmented into multiple lower sample rate ADCs operating in parallel with time-interleaved configuration. Each ADC handles a portion of the sampling tasks, and their outputs are combined to achieve the overall high sample rate while using slower, less expensive components
Solution Approach 2:
Correction coefficients are applied to dynamically adjust and equalize parameters (bandwidth, sampling time, gain, offset) of the individual ADCs. These coefficients modify the operating parameters of each ADC to compensate for manufacturing variations and ensure consistent dynamic performance across all channels
2Device complexity
If standard ADC components are used without calibration, then device complexity is reduced, but intermodulation distortion increases due to parameter mismatch
Solution Approach 1:
Correction coefficients are determined and stored in memory elements before the ADC operates in normal mode. This preliminary calibration phase measures the actual parameters of each ADC and computes the necessary correction values, which are then applied during operation to eliminate intermodulation distortion
Solution Approach 2:
The system incorporates a feedback mechanism where the output of the time-interleaved ADC is analyzed to determine correction coefficients. These coefficients are fed back to adjust the operation of individual ADCs, creating a closed-loop system that continuously optimizes performance and minimizes distortion
Data Source
AI summary
A time interleaving Analog-to-Digital Converter (ADC) comprises a plurality of ADCs; a timing generator that generates a clock signal for each of the ADCs such that edges of said clock signals trigger sampling of an input signal by the ADCs; and a timing adjustment circuit to receive and adjust the clock signals before the clock signals are received by the ADCs such that samplings of said input signal are spaced in time and occur at a rate of 1/N times a desired sampling rate; and circuit for adjusting the bandwidth of the plurality of ADCs.