ADC Sample Timing Calibration for Cellular Modem RF Measurements

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current wireless modems face uncertainty in Analog-to-Digital Converter (ADC) timing due to accumulated delay in the ADC input clock generation path, affecting the accuracy of RF signal measurements and subsequent positioning in mobile communication networks.

Innovation Solution

Incorporating a switch at the ADC input terminal to route the system clock directly for timing determination and then switching to route analog RF signals for regular sampling, allowing for accurate ADC output timing calculation based on both methods.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the ADC input clock generation path is used for timing determination, then the ADC can operate normally, but accumulated delay in the clock generation path causes timing uncertainty and measurement inaccuracy

Engineering Contradiction:

ImproveADC timing accuracyVSAvoidRF signal measurement accuracy

Core Design Contradiction:

ReliabilityVSMeasurement precision

Solution Approach 1:

The patent segments the ADC operation into two distinct modes: a first mode for timing determination where the switch routes the ADC input clock directly to the ADC input, and a second mode for normal operation where the switch routes analog RF signals to the ADC input. This segmentation allows independent optimization of timing accuracy and measurement functionality.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces a switch as an intermediary component that controls the signal routing to the ADC input. The switch enables selective connection between the ADC input clock signal and analog RF signals, allowing the system to choose the appropriate input source based on the operational mode, thereby eliminating timing uncertainties.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of operation

If a long ADC input clock generation path is used, then the ADC can be clocked properly, but accumulated delay in the path leads to timing uncertainty

Engineering Contradiction:

ImproveADC clock generationVSAvoidADC output timing accuracy

Core Design Contradiction:

Ease of operationVSLoss of time

Solution Approach 1:

The patent performs preliminary timing determination by routing the ADC input clock directly to the ADC input in a first mode before normal operation. This preliminary action measures and establishes the timing characteristics of the ADC output samples, allowing the system to compensate for any delays in the clock generation path during subsequent normal operation.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS11929766B2Obtaining accurate timing of analog to digital converter samples in cellular modem

Publication Date: 2024.03.12 QUALCOMM INC

AI summary

According to embodiments, an example method for determining an analog-to-digital converter (ADC) output timing in a user equipment may include operating a switch in a first mode to route a system clock from an oscillator to an input of the ADC and determining a first ADC output timing based on a first set of ADC samples generated by the ADC. The method may also include operating the switch in a second mode to route analog signals from a transceiver of the user equipment to the input of the ADC and obtaining a second set of ADC samples generated by the ADC based on the analog signals.