ADC Timing Loop Compensation for Phase-Stable Signal Recovery
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional timing recovery systems for optical storage devices suffer from phase shifts and non-linearity issues due to adaptive filters, which compromise timing signal performance and are affected by manufacturing defects in optical media.
Innovation Solution
A timing generation and compensation circuit that includes a slicer bias loop and a limit equalizer to compensate for asymmetrical qualities in ADC output, decoupling the timing loop from filter adaptation and reducing phase distortion, while using a novel phase rotator and bias error detector to improve timing recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a filter (such as a FIR filter) is used to provide signal equalization to the ADC output, then signal equalization performance is improved, but the timing signal experiences phase shift and compromised performance
Solution Approach 1:
The system separates the timing signal extraction path from the filtered signal path. The timing signal is derived directly from the ADC output before filtering, while the filtered signal goes to the detector. This segmentation eliminates the phase shift problem caused by filtering the timing signal while maintaining signal equalization benefits.
Solution Approach 2:
A dedicated timing signal extraction circuit is introduced as an intermediary component that processes the ADC output independently from the main signal path. This intermediary extracts the timing signal before it enters the filter, preventing the filter from affecting timing signal phase while still allowing the filter to improve signal equalization for the detector.
2Adaptability or versatility
If the filter is designed to be adaptive to density variation and focus offsets, then equalization performance is improved, but the timing signal undergoes phase change
Solution Approach 1:
The system divides the signal processing into two independent paths: one for timing signal extraction that bypasses the adaptive filter, and another for signal equalization that uses the adaptive filter. This allows the filter to adapt to density variations and focus offsets without affecting timing signal phase stability.
3Ease of manufacture
If manufacturing defects such as pit size variations are present in optical storage devices, then device production is simplified, but non-linearity defects cause deterioration of timing loop performance
Solution Approach 1:
The system employs a feedback mechanism where the timing error signal is used to adjust the timing recovery, compensating for non-linearity defects caused by manufacturing variations. The feedback loop continuously corrects timing errors resulting from pit size variations and other manufacturing defects.
Solution Approach 2:
The timing loop performs self-correction by using its own output to adjust its performance. The timing error detector and loop filter work together to automatically compensate for non-linearity defects without requiring external intervention, maintaining timing loop performance despite manufacturing variations.
Data Source
AI summary
A device and process to compensate for asymmetrical qualities of an analog input signal, if present, and generate a timing signal. The timing signal is then used for analog to digital conversion.