Successive Approximation ADC Timing for Low-Power Conversion
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Solution Overview
Problem
The existing successive approximation type AD converter circuits face challenges in setting optimal sampling and comparison periods, leading to increased energy consumption and power consumption due to fixed comparison periods and fixed comparator currents, especially when dealing with high impedance analog signal sources.
Innovation Solution
The proposed solution involves a successive approximation type AD converter circuit with separate clock signals for determining sampling and comparison periods, allowing for independent setting of these periods and optimizing the comparator current through software registration, thereby maximizing the sampling period while keeping the comparison period within acceptable limits and minimizing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the comparison period is fixed and comparator current is fixed, then the circuit structure is simple, but the energy consumption increases and power consumption increases
Solution Approach 1:
The patent divides the single clock signal into two separate clock signals: one for the sampling period and another for the comparison period. This segmentation allows independent control of each period, enabling the comparison period to be shortened and comparator current to be reduced, thereby lowering energy consumption while maintaining circuit functionality.
Solution Approach 2:
The patent introduces dynamic control mechanisms including a sampling period setting unit and a comparison period setting unit that can independently adjust the duration of sampling and comparison phases. Additionally, a comparator current setting unit dynamically adjusts comparator current based on signal characteristics, optimizing energy consumption adaptively.
2Measurement precision
If the sampling period is extended for high impedance analog signal sources, then the conversion accuracy improves, but the comparison period also increases leading to higher power consumption
Solution Approach 1:
By separating the sampling period and comparison period with different clock signals, the patent allows the sampling period to be extended for accurate charging of high impedance sources while the comparison period can be independently shortened, preventing proportional increase in power consumption.
Solution Approach 2:
The patent changes the parameter of comparator current from fixed to variable, adjusting it based on the actual comparison needs. This allows the system to use lower current during comparisons even when sampling periods are extended, decoupling the relationship between sampling duration and power consumption.
3Device complexity
If the same clock signal is used for both sampling and comparison, then the circuit is simpler, but the sampling period and comparison period cannot be optimized independently
Solution Approach 1:
The patent segments the clock signal system into two independent clock signals with separate setting units, enabling flexible and independent optimization of sampling period and comparison period while maintaining relatively simple circuit architecture.
Solution Approach 2:
The patent creates a multi-functional clock management system where separate clock signals serve different purposes (sampling vs. comparison), allowing the AD converter to adapt to various application requirements with different timing needs without requiring completely different circuit designs.
Data Source
AI summary
A successive approximation type AD converter circuit for comparing an analog input signal with an output analog signal of a DA converter with a comparator to input a digital signal output in accordance with a comparison result to the DA converter to determine a digital signal obtained if the output analog signal of the DA converter is equal to the analog input signal, as an AD-converted output signal, includes: an AD converter for AD-converting the analog input circuit in accordance with a sampling period for sampling the analog input signal and a comparison period for comparing the sampled analog input signal with the output analog signal of the DA converter with the comparator; and setting means for independently setting a cycle time of a first clock signal for determining the sampling period and a cycle time of a second clock signal for determining the comparison period.