ADC Timing Control with Programmable Delay for Ripple Reduction
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Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) experience supply voltage ripple due to loading by multiple sources during operation, which affects conversion accuracy and requires larger decoupling capacitors, increasing IC area.
Innovation Solution
A timing control circuitry is implemented in ADCs, comprising a regulator circuit, comparator circuit, and programmable delay circuit, where a controller adjusts the clock signal based on operating parameters like temperature and trim data to align conversion cycles, reducing ripple and allowing smaller decoupling capacitors, thus minimizing IC area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If larger decoupling capacitors are used to reduce voltage ripple, then voltage ripple is reduced and ADC accuracy is improved, but IC area increases
Solution Approach 1:
The patent applies preliminary action by pre-scheduling conversion operations to be distributed across different ping-pong phases. The converter is configured to perform first conversions during first ping-pong phases and second conversions during second ping-pong phases, before the actual conversion occurs. This advance timing arrangement prevents simultaneous loading of the decoupling capacitor, reducing voltage ripple without requiring larger capacitor size.
2Productivity
If multiple conversion operations are performed simultaneously, then productivity is improved, but voltage ripple increases due to supply loading
Solution Approach 1:
The patent applies segmentation by dividing conversion operations into separate ping-pong phases. First conversions and second conversions are scheduled in different phases, with at least one intermediate phase between them. This temporal segmentation distributes the supply loading across different time periods, maintaining high productivity while reducing voltage ripple caused by simultaneous operations.
3Productivity
If conversion cycle time is reduced for high-speed operation, then productivity is improved, but timing precision becomes more critical and harder to control
Solution Approach 1:
The patent applies dynamics by making the operation schedule configurable and adaptable. The converter can be configured to perform conversions at different rates and with different timing arrangements between ping-pong phases. This dynamic scheduling allows optimization for both high-speed operation and timing precision control, accommodating different application requirements without compromising either productivity or timing accuracy.
Data Source
AI summary
In a described example, a circuit includes a regulator circuit having a regulator output. A comparator circuit includes a voltage input, a clock input, and a signal output, in which the voltage input is coupled to the regulator output. A clock generator circuit has a second voltage input and the clock generator includes a programmable delay circuit, the programmable delay circuit having a signal input, a control input, and a clock output, in which the second voltage input is coupled to the regulator output, the signal input is coupled to the signal output, the clock output is coupled to the clock input. A controller includes a control output coupled to the control input.