ADC Transition Timing Detection for Product-Sum Signal Conversion
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Solution Overview
Problem
Existing semiconductor integrated circuits face challenges in efficiently performing product-sum operations required for machine learning, particularly in converting multi-value data from hardware-based operations into digital signals for accurate processing.
Innovation Solution
A semiconductor integrated circuit with a digital signal generator and transition timing detector that generates binary signals based on discharge amounts, allowing for accurate identification of product-sum operation values by monitoring the timing of logic transitions in the circuit's bit lines, eliminating the need for complex comparators and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multi-value data is used to represent product-sum operation results, then processing accuracy is improved, but device complexity increases due to the need for complex comparators and multiple potential level identification circuits
Solution Approach 1:
The patent converts the representation parameter of product-sum operation results from multi-value data with multiple potential levels to binary data with two potential levels. This parameter change simplifies the identification circuit from complex multi-level comparators to simple binary detection circuits, resolving the contradiction between measurement precision and device complexity
Solution Approach 2:
The patent extracts only the necessary information (timing of logic transition) from the multi-value product-sum operation result, discarding the complex multi-level representation. By taking out only the essential timing information and representing it in binary form, the circuit complexity is reduced while preserving the ability to identify operation values accurately
2Measurement precision
If complex comparator circuits are used to convert potential levels to digital signals, then conversion accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces expensive, power-consuming complex comparator circuits with simple, low-power binary detection circuits. The binary logic transition detection circuit consumes significantly less power while maintaining conversion accuracy, effectively using a simpler 'cheaper' solution to resolve the contradiction
Solution Approach 2:
By changing the output parameter from multi-level digital signals to binary digital signals, the patent enables the use of low-power binary detection logic instead of high-power comparator circuits, resolving the contradiction between conversion accuracy and power consumption
3Productivity
If hardware-based product-sum operation is implemented, then processing speed is improved, but circuit area increases due to additional conversion circuits
Solution Approach 1:
The patent extracts only the essential timing information from the product-sum operation result and represents it in binary form. This extraction approach eliminates the need for large-area complex conversion circuits, reducing circuit area while maintaining hardware-based fast processing capability
Solution Approach 2:
By changing the data representation parameter to binary, the patent reduces the circuit area required for signal conversion. Binary logic circuits occupy significantly less area than multi-level comparator circuits, resolving the contradiction between processing speed and circuit area
Data Source
AI summary
A semiconductor integrated circuit has a digital signal generator that generates a binary signal whose logic transitions at a timing according to a discharge amount of a second wiring which is discharged when multiplication data of first data stored in a memory cell and second data on a first wiring is a first logic; and a transition timing detector that detects a timing at which the logic of the binary signal transitions.