ADC Sampling Clock Circuit Using Variable Resistance Delay Tuning
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Solution Overview
Problem
The existing sampling clock generating circuits for ADC chips face a timing offset issue due to limitations in phase inverter delays, leading to non-uniform interlaced sampling and reduced conversion precision.
Innovation Solution
A sampling clock generating circuit incorporating a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where the resistance value changes at intervals, allowing for precise adjustment of the timing offset by maintaining the output signal at a high level for a controlled duration, effectively canceling timing offsets between sampling points.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If phase inverters are connected in series in transmission channels to obtain sampling clocks at different phases, then multiple ADC chips can perform interlaced sampling, but timing offset between sampling points cannot be effectively adjusted due to limited delay capability (only as low as 20 ps)
Solution Approach 1:
The patent changes the physical parameter of delay time by replacing fixed phase inverters with a variable delay circuit. This circuit uses a plurality of delay elements (such as buffers or transmission gates) that can be dynamically controlled to adjust the delay time of clock signals, enabling precise timing offset adjustment beyond the limited 20 ps capability of traditional phase inverters.
Solution Approach 2:
The patent introduces dynamic adjustability to the clock signal generation system. By using controllable delay elements that can be programmed or tuned in real-time, the system transitions from fixed delay (phase inverters) to dynamic delay adjustment, allowing the timing offset to be optimized for different operating conditions and achieving sub-10 ps precision.
2Device complexity
If fixed delay is used in transmission channels, then circuit structure is simple, but interlaced sampling becomes non-uniform and harmonic occurs reducing ADC conversion precision
Solution Approach 1:
The patent transforms the fixed delay parameter into a variable parameter. By implementing a variable delay circuit with multiple controllable delay stages, the system can dynamically adjust the delay time to achieve uniform interlaced sampling across multiple ADC chips, eliminating the sampling non-uniformity and harmonic distortion caused by fixed delay while maintaining reasonable circuit complexity.
3Productivity
If multiple ADC chips are used for interlaced sampling to achieve higher sampling frequency, then productivity increases, but timing offset between channels causes harmonic distortion and reduces conversion precision
Solution Approach 1:
The patent implements a feedback mechanism where the actual timing of sampling points from multiple ADC chips is measured and compared against the ideal timing. Based on this feedback, the variable delay circuit adjusts the clock signal delay for each channel to compensate for timing offsets, thereby eliminating harmonic distortion and maintaining high conversion precision while achieving higher sampling frequencies through interlaced sampling.
Data Source
AI summary
A sampling clock generating circuit and an analog to digital converter (ADC) includes a variable resistance circuit, a NOT-gate type circuit, and a capacitor, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T, an output end of the NOT-gate type circuit is coupled to one end of the capacitor, the other end of the capacitor is grounded, a power supply terminal of the NOT-gate type circuit is connected to a power supply, a ground terminal of the NOT-gate type circuit is coupled to one end of the variable resistance circuit, and the other end of the variable resistance circuit is grounded, the NOT-gate type circuit is configured to output a low level when the pulse signal is a high level, and output a high level when the pulse signal is a low level.