Add-on Memory Coherence Directory for Scalable Multi-Processor Systems
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Solution Overview
Problem
Current multiple processor data processing systems face scalability issues with snoopy-based memory coherence protocols, which become inefficient as system size increases, necessitating a transition to directory-based protocols but is costly and resource-intensive.
Innovation Solution
Implementing an add-on memory coherence directory that selectively uses a directory protocol for memory regions with limited sharing and a snoopy protocol for regions with extensive sharing, allowing for an incremental transition from snoopy to directory-based protocols, with a programmable threshold to define limited sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a snoopy protocol is used for memory coherence, then all processors can monitor all memory requests, but the system becomes inefficient and does not scale as system size increases
Solution Approach 1:
The patent segments the memory coherence management by dividing memory regions into different sharing categories (limited sharing vs. extensive sharing). Directory-based protocol is applied to regions with limited sharing, while snoopy protocol is used for regions with extensive sharing. This segmentation allows the system to maintain coherence reliably while scaling efficiently, as each protocol is applied only where appropriate.
Solution Approach 2:
The patent implements dynamic protocol selection based on runtime sharing patterns. The system monitors memory access patterns and dynamically adjusts which protocol (directory-based or snoopy) is used for each memory region. This dynamic adaptation allows the system to optimize for both coherence reliability and scalability as sharing patterns change during execution.
2Productivity
If a directory-based protocol is used for memory coherence, then system scalability is improved, but the cost and resource consumption increase significantly
Solution Approach 1:
The patent applies local quality by using directory-based protocol only for memory regions with limited sharing (where it provides scalability benefits) while retaining snoopy protocol for regions with extensive sharing (where it is more cost-effective). This localized application of different protocols reduces overall system complexity and resource consumption while maintaining scalability where needed.
Solution Approach 2:
The patent implements partial action by applying directory-based coherence management only to the extent necessary - specifically to memory regions with limited sharing. Rather than implementing directory-based protocol system-wide (which would be excessive and costly), the system applies it partially only where scalability improvements are most beneficial, thereby reducing implementation costs while maintaining scalability advantages.
3Productivity
If directory-based protocol is used for all memory regions, then scalability is enhanced, but overhead increases for memory regions that would benefit more from snoopy protocol
Solution Approach 1:
The patent applies local quality by matching protocol selection to local memory region characteristics. Memory regions with limited sharing receive directory-based protocol (where scalability overhead is justified), while regions with extensive sharing receive snoopy protocol (where overhead is minimized). This local optimization reduces overall energy consumption and protocol overhead while preserving scalability benefits where they are most valuable.
Data Source
AI summary
A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory access resulting in a cache miss in a given processor, the processor determines whether a memory region being accessed is marked as directory-based. Responsive to the given processor determining the memory region is marked as directory-based, the given processor accesses a directory entry corresponding to the memory region to identify a home chip for the page using a directory-based protocol. The given processor forwards the memory access request to the home chip to perform the memory access.