Adder Array Rearrangement for Multiply-Accumulate Efficiency
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Solution Overview
Problem
Existing data processing systems face inefficiencies in executing multiply-and-accumulate-products (MAP) instructions, particularly in terms of circuit area and power consumption, due to the need for extensive adder circuitry and increased complexity as the number of MAP operations varies.
Innovation Solution
The system employs a rearrangement operation to align E×F products with a subset of adders within the adder array, allowing reuse of columns for different numbers of MAP operations, thereby reducing the required adder circuitry and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If extensive adder circuitry is used to execute MAP instructions, then the number of MAP operations that can be performed increases, but circuit area and power consumption increase
Solution Approach 1:
The adder array is designed to perform multiple functions: it can execute standard multiplication operations and MAP operations using the same hardware resources. By configuring the adder array to accumulate partial products for MAP operations without requiring dedicated adder columns, the system achieves multi-functionality that reduces overall circuit area while maintaining the capability to perform multiple MAP operations in parallel
Solution Approach 2:
The system dynamically configures the operation mode of the adder array based on the instruction type. For MAP operations, the adder array is configured to accumulate products with selective enabling of adder columns based on the parameter N, allowing the circuit to adapt its behavior and resource usage dynamically without requiring fixed dedicated hardware for each operation type
2Adaptability or versatility
If more adder columns are provided to handle varying numbers of MAP operations, then adaptability increases, but device complexity and circuit area increase
Solution Approach 1:
The same adder array structure serves both standard multiplication and MAP operations, eliminating the need for separate dedicated adder columns for MAP operations. This universal design provides adaptability to different numbers of MAP operations while avoiding the complexity increase that would result from providing separate adder columns for each operation type
Solution Approach 2:
The system uses a parameter N to control the number of MAP operations, and this parameter dynamically adjusts the enabling of adder columns and the configuration of the adder array. This parameter-driven approach provides adaptability without requiring complex hardwired logic for each possible configuration, as the parameter N controls the behavior through simple enabling/disabling mechanisms
3Productivity
If additional adder components are added to support MAP operations, then the capability to perform MAP operations improves, but power consumption increases
Solution Approach 1:
The adder array performs both standard multiplication and MAP operations using the same hardware, eliminating the need for additional dedicated adder components for MAP operations. This reuse of existing adder infrastructure provides MAP operation capability without the power consumption penalty of adding separate dedicated hardware
Solution Approach 2:
The adder array continuously accumulates partial products for MAP operations without requiring additional adder stages, maintaining the continuous useful action of product accumulation. By reusing the existing adder array for MAP operations rather than adding separate adder components, the system maintains continuous operation while avoiding the power consumption increase that would result from additional active adder components
Data Source
AI summary
An apparatus and method are provided for performing multiply-and-accumulate-products (MAP) operations. The apparatus has processing circuitry for performing data processing, the processing circuitry including an adder array having a plurality of adders for accumulating partial products produced from input operands. An instruction decoder is provided that is responsive to a MAP instruction specifying a first J-bit operand and a second K-bit operand, to control the processing circuitry to enable performance of a number of MAP operations, where the number is dependent on a parameter. For each performed MAP operation, the processing circuitry is arranged to generate a corresponding result element representing a sum of respective E×F products of E-bit portions within an X-bit segment of the first operand with F-bit portions within a Y-bit segment of the second operand, where E<X≤J and F<Y≤K. In response to the MAP instruction, the instruction decoder is configured to control the processing circuitry to perform a rearrangement operation to rearrange the portions of at least one of the first operand and the second operand to form transformed first and second operands so that the E×F products that are required to be summed are aligned with a number of columns of adders within the adder array. Further, the adder array is controlled in dependence on the transformed first and second operands to add the required E×F products using the number of columns of adders within the adder array. Further, the rearrangement performed by the rearrangement operation is controlled in dependence on the parameter such that at least one column of adders used when the parameter indicates the first number of MAP operations is reused when the parameter indicates a second number of MAP operations different to the first number. This provides a particularly area and power efficient implementation for handling MAP operations.