Adder-Based Horizontal Minimum Circuit for Single-Cycle Comparison
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Solution Overview
Problem
Conventional microprocessors require multiple cycles to determine the horizontal minimum of a set of digital values, which increases circuitry complexity and costs, and reduces processing efficiency.
Innovation Solution
A system and method utilizing first and second adders and a compare circuit to determine the minimum of binary values in a single cycle, with additional difference circuits, a routing circuit, and a compare circuit to compare multiple digital values efficiently, allowing for the integration of the horizontal minimum instruction on a microprocessor chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple magnitude comparators are used to identify the minimum value in a single cycle, then the processing speed is improved, but the circuit complexity and die space increase significantly
Solution Approach 1:
The patent makes the adder circuit perform multiple functions: it serves as both an arithmetic addition unit and a comparison unit. By interpreting the carry outputs and propagate outputs from the adder in different ways depending on the instruction type, the same hardware circuitry is used for both addition and minimum value detection operations, eliminating the need for separate comparator circuits.
Solution Approach 2:
The patent changes the interpretation parameters of the adder outputs based on the instruction type. For PHADD instructions, the carry and propagate outputs are interpreted one way to determine sum values, while for PHMINPOSUW instructions, the same outputs are interpreted differently to determine minimum values and their positions, allowing a single circuit to handle multiple operations.
2Productivity
If multiple magnitude comparators are used to identify the minimum value in a single cycle, then the processing efficiency is improved, but the manufacturing cost increases
Solution Approach 1:
The adder circuit is designed to be universal, handling both PHADD and PHMINPOSUW instructions with the same hardware resources. This multi-functionality reduces the total component count on the microprocessor die, thereby lowering manufacturing costs while maintaining high processing efficiency for both instruction types.
Solution Approach 2:
The patent merges the addition function and comparison function into a single integrated circuit unit. By combining these previously separate functions into one adder-based structure, the overall circuit complexity is reduced, leading to lower manufacturing costs and simpler fabrication processes.
3Device complexity
If multiple cycles are used to determine the horizontal minimum, then the circuit complexity is reduced, but the processing time increases
Solution Approach 1:
The patent uses feedback from the adder's carry and propagate outputs to directly determine both the minimum value and its position in a single cycle. The carry chain information is fed back and interpreted to identify which input operand contains the minimum value, eliminating the need for multiple sequential comparison cycles while keeping the circuit relatively simple.
Solution Approach 2:
The adder circuit performs preliminary computation during the normal addition operation, generating carry and propagate signals that contain embedded comparison information. This preliminary action allows the minimum value detection to occur simultaneously with the addition operation rather than requiring separate sequential comparison steps.
Data Source
AI summary
A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digital value and provides a first carry output and a propagate output. The second adder compares lower bits of the first digital value with lower bits of the second digital value and provides a second carry output. The compare circuit determines whether the first digital value is greater than the second digital value based on the carry and propagate outputs. Multiple difference circuits may be used to compare each of multiple digital values with every other digital value to provide corresponding compare bits, which are then used to determine a minimum one of the digital values and its corresponding location.