Adder with Reduced Capacitance via Differential Buffer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The propagation delay in carry propagate circuits of full adder circuits is significant, impacting the speed and efficiency of logic operations in electronic circuits, particularly in multi-bit addition processes.
Innovation Solution
The implementation of a differential buffer circuit within the carry propagate circuit to decouple input capacitance, reducing the capacitive load and sharing it more evenly between inverters, thereby reducing the propagation delay and increasing the speed of signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a standard full adder circuit is used to perform logic operations, then the circuit can implement basic addition functions, but the propagation delay through the carry propagate circuit becomes significant and limits the speed of operation
Solution Approach 1:
The carry propagate circuit is segmented into multiple parallel paths: a direct carry path and an indirect path through the sum logic. This segmentation allows the carry signal to propagate through different routes simultaneously, reducing the overall propagation delay by avoiding a single long critical path.
Solution Approach 2:
The patent introduces intermediary logic elements and alternative signal paths that mediate the carry propagation process. By adding intermediate stages and parallel pathways, the carry signal can bypass the bottleneck of the traditional sequential logic path, thereby reducing propagation delay.
2Productivity
If the input capacitance of the summing circuit is directly connected to the carry propagate circuit, then the logic function is implemented, but the capacitive load on the carry line increases and slows down signal propagation
Solution Approach 1:
The patent extracts the capacitive load from the carry propagate circuit by separating the sum logic input capacitance from the carry path. This is achieved by introducing alternative signal routing where the carry signal does not directly drive the full input capacitance of the summing circuit, thereby reducing the capacitive burden on the carry line and improving propagation speed.
3Adaptability or versatility
If multiple full adder cells are connected in series to perform multi-bit addition, then higher order addition is achieved, but the total propagation delay increases significantly due to the cumulative effect of each cell's delay
Solution Approach 1:
When multiple full adder cells are connected in series, each cell is segmented to provide parallel carry propagation paths. This segmentation ensures that the carry signal can propagate through adjacent cells simultaneously via multiple routes, preventing the cumulative delay from adding up linearly and instead allowing for parallel processing of carry signals across the adder chain.
Solution Approach 2:
The patent extends the carry propagation into another dimension by creating a two-dimensional network of carry paths rather than a simple one-dimensional chain. This allows carry signals to propagate through adjacent cells in parallel through multiple dimensional pathways, significantly reducing the total propagation delay for multi-bit addition.
Data Source
AI summary
An electronic circuit for performing logic operations is provided. The electronic circuit comprises a logic gate having at least two binary inputs adapted to receive corresponding input binary digits; an output for outputting an output signal; signal transmission means between said input and said output; a logic circuit coupled to said transmission means and having an input capacitance, and capacitance decoupling means between said logic circuit and said transmission means for decoupling the input capacitance of said logic circuit from said transmission means.