Adder-Rounder Circuitry for Programmable Logic Device

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Existing digital signal processing (DSP) blocks in programmable logic devices (PLDs) have limited rounding capabilities, which restrict their efficiency and flexibility in performing complex mathematical operations.

Innovation Solution

The implementation of specialized processing blocks with fundamental processing units that combine the functionality of multiple multipliers and adders, along with flexible rounding circuitry that allows for user-selectable rounding modes and bit positions, enabling simultaneous addition and rounding within a single clock cycle.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If separate multipliers and adders are used in DSP blocks, then individual multiplication operations can be performed independently, but the area required increases and processing efficiency decreases

Engineering Contradiction:

Improveprocessing efficiencyVSAvoidarea of specialized processing block

Core Design Contradiction:

ProductivityVSArea of stationary object

Solution Approach 1:

The patent combines multiple multipliers and adders into a single integrated fundamental processing unit. Specifically, two 18x18 multipliers and one adder are merged into one unit that computes the sum of two multiplication operations in a single step, reducing the area required compared to separate implementations while improving processing efficiency.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The fundamental processing unit is designed to perform multiple functions: it can compute the sum of two multiplication operations, perform single multiplication operations (by zeroing inputs to one multiplier), and support various multiplication sizes (18x18, 9x9, 12x12). This multi-functionality reduces the need for separate dedicated circuits for each operation type.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If limited rounding capabilities are provided in DSP blocks, then device complexity is reduced, but adaptability for different digital signal processing operations is restricted

Engineering Contradiction:

Improverounding capability flexibilityVSAvoidcomplexity of rounding circuitry

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The rounding circuitry is designed to be dynamically configurable, allowing users to select different rounding modes (rounding to nearest integer, rounding to nearest even, truncation) and choose from multiple available bit positions for rounding. This dynamic adaptability enables the same circuit to handle various digital signal processing operations with different rounding requirements without requiring separate dedicated circuits for each mode.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS7822799B1Adder-rounder circuitry for specialized processing block in programmable logic device

Publication Date: 2010.10.26 TAHOE RES LTD

AI summary

Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.