Adder Tree Layout Using Mixed-Strength Full Adders
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Solution Overview
Problem
Existing adder trees in binary arithmetic circuits face challenges in achieving a balance between silicon area, power consumption, and speed, particularly when using full adders with varying driving strengths.
Innovation Solution
The implementation of an adder tree structure that interleaves full adders with different transistor counts, specifically 28-transistor and 14-transistor adders, arranged in specific patterns to optimize silicon area and power consumption while maintaining speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If full adders with stronger driving strength (more transistors) are used throughout the adder tree, then speed is improved, but silicon area and power consumption increase
Solution Approach 1:
The patent applies local quality by assigning different driving strengths to different positions within the adder tree. Specifically, full adders near the root node use stronger driving strength (28 transistors) to ensure fast signal propagation, while full adders at lower levels use weaker driving strength (14 transistors). This localized differentiation optimizes overall performance by concentrating resources where they are most needed for speed-critical paths, while reducing silicon area and power consumption in less critical regions.
2Speed
If full adders with stronger driving strength (more transistors) are used throughout the adder tree, then speed is improved, but power consumption increases
Solution Approach 1:
The patent implements local quality by varying the driving strength of full adders based on their position in the adder tree. Full adders closer to the root node (which critically affect overall speed) are equipped with stronger driving strength (28 transistors), while those farther away use weaker driving strength (14 transistors). This localized approach ensures that power consumption is concentrated in regions that most impact speed performance, thereby achieving acceptable speed while minimizing total power consumption across the entire adder tree.
3Area of stationary object
If full adders with weaker driving strength (fewer transistors) are used throughout the adder tree, then silicon area and power consumption are reduced, but speed decreases
Solution Approach 1:
The patent resolves this contradiction by applying local quality principles: full adders positioned at critical locations near the root node use stronger driving strength (28 transistors) to maintain high speed performance, while full adders at non-critical lower levels use weaker driving strength (14 transistors) to reduce silicon area. This spatial differentiation ensures that speed is optimized where it matters most, while achieving area reduction in less speed-critical regions.
4Device complexity
If a uniform adder structure is used throughout the adder tree, then design simplicity is maintained, but optimization of silicon area and power consumption is limited
Solution Approach 1:
The patent applies local quality by introducing structural variation in the adder tree: full adders near the root node use a 28-transistor design with stronger driving strength, while full adders at lower levels use a 14-transistor design with weaker driving strength. This localized structural differentiation optimizes silicon area by reducing transistor count in non-critical regions, while maintaining design manageability through a systematic pattern of variation rather than complete heterogeneity.
Data Source
AI summary
In some aspects of the present disclosure, an adder tree circuit is disclosed. In some aspects, the adder tree circuit includes a plurality of full adders (FAs) including: a first subgroup of FAs, wherein each FA of the first subgroup includes a first number of transistors; and a second subgroup of FAs, wherein each FA of the second subgroup includes a second number of transistors, the first number being greater than the second number; wherein each FA of the first subgroup receives a first input from a first one of the second subgroup of FAs and a second input from a second one of the second subgroup of FAs, and each FA provides a first output to a third one of the second subgroup of FAs and a second output to a fourth one of the second subgroup of FAs.