Additive Interconnect Formation for Sub-8 Nm Metal Lines
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Solution Overview
Problem
At modern process nodes, forming metal lines with critical dimensions less than 8 nm is challenging due to line edge roughness and the inability to avoid line breaks, shorts, and flop overs in conventional subtractive lithography and etching processes, which affects electrical performance.
Innovation Solution
An additive interconnect formation process involving a semiconductor substrate with a metal via and a metal line less than 8 nm wide and at least 20 nm tall, where a metal-containing liner is deposited and anisotropically etched to define separate portions for growing a metal line with reduced line edge roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional subtractive lithography and etching processes are used to form metal lines, then manufacturing capability is maintained, but line edge roughness increases and manufacturing precision deteriorates for lines less than 8 nm wide
Solution Approach 1:
The patent inverts the conventional subtractive approach by using an additive process: metal lines are formed by selective deposition on exposed portions of a liner rather than by etching away material. This reversal enables precise control of line edges through deposition thickness control, achieving line edge roughness of less than 1 nm while maintaining manufacturing capability for sub-8 nm lines
Solution Approach 2:
The patent performs preliminary actions by first forming a liner layer and selectively exposing portions of it before depositing the metal line. This preliminary exposure and liner formation creates a precise template that guides subsequent metal deposition, ensuring accurate line placement and edge definition before the actual metal line formation occurs
2Reliability
If conventional subtractive processes are used for metal line formation, then existing manufacturing processes are utilized, but line breaks and shorts occur due to edge roughness
Solution Approach 1:
By inverting from subtractive to additive processing, the patent eliminates the edge roughness that causes line breaks and shorts. The additive deposition process naturally produces smooth line edges with roughness of less than 1 nm, ensuring line continuity and reliability for sub-8 nm metal lines without the defects inherent in conventional etching approaches
3Manufacturing precision
If photolithographic subtractive manufacturing is used at scales less than the wavelength of light, then conventional manufacturing methods are applied, but feature size reduction is limited and line bridges and breaks occur
Solution Approach 1:
The patent bypasses the fundamental limitation of photolithography by inverting to an additive approach. Instead of using light to pattern photoresist and then etch, the method uses selective deposition on exposed liner portions to form metal lines. This enables precise feature size control and maintains line integrity for dimensions below the light wavelength, achieving sub-8 nm lines without the bridges and breaks that plague conventional methods
Solution Approach 2:
The patent replaces the optical-mechanical photolithography-etching system with a purely additive deposition system. By substituting the optical patterning mechanism with selective deposition on pre-exposed liner structures, the method achieves superior precision and reliability for sub-wavelength feature sizes, eliminating the fundamental diffraction limits of photolithography
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enables the reliable formation of metal lines with less than 1 nm line edge roughness and prevents line breaks and shorts, improving conductivity and reducing edge roughness compared to subtractive processes.
Implementation Method 1
depositing a metal-containing liner onto the mandrel
Implementation Method 2
exposing the top of the mandrel by anisotropically etching the liner
Implementation Method 3
growing a metal line on each portion of the liner
Data Source
AI summary
A semiconductor substrate has a metal via in the substrate, and has, on the substrate, a metal line that is less than 8 nanometers (nm) wide and at least 20 nm tall. A method for making a semiconductor structure includes forming a metal via in a substrate; forming a mandrel atop and offset from the via; depositing a metal-containing liner onto the mandrel; exposing the top of the mandrel by anisotropically etching the liner, thereby defining a separate portion of the liner at each side of the mandrel; and growing a metal line on each portion of the liner.