Additive Microelectronic Substrate Fabrication for Doped Semiconductor Integration
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Solution Overview
Problem
The challenge in microelectronic device fabrication lies in integrating diverse components with varying structural and dopant requirements, leading to increased complexity and cost due to the need for multiple process steps, often resulting in compromised performance and reliability.
Innovation Solution
The use of additive processes to form semiconductor regions and structures with specific conductivity types and dopant densities, allowing for concurrent formation of structural elements with varying characteristics without the need for photolithographic or ion implant operations, thereby reducing fabrication costs and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional fabrication processes (lithography, ion implant) are used to form diverse semiconductor structures with different dopant and spatial requirements, then various component types can be integrated, but the number of process steps increases, leading to increased fabrication cost and complexity
Solution Approach 1:
The patent applies parameter changes by varying dopant concentration, conductivity type, and spatial distribution within a unified additive manufacturing process. Different semiconductor structures are formed by adjusting material composition and deposition parameters rather than through multiple discrete process steps, thereby maintaining versatility while reducing complexity
Solution Approach 2:
The additive manufacturing process serves as a universal method that can form various semiconductor structures (source/drain regions, wells, isolation structures) with different dopant requirements in a single integrated process flow, eliminating the need for separate lithography and ion implantation steps for each structure type
2Device complexity
If structural elements of different component types are formed concurrently with compromised dopant and spatial values, then fabrication complexity is reduced, but performance and reliability of the microelectronic device deteriorates
Solution Approach 1:
The patent implements local quality by enabling different dopant concentrations, conductivity types, and spatial configurations to be precisely controlled at different locations within the substrate using additive manufacturing. Each semiconductor structure receives optimized material deposition parameters tailored to its specific requirements, ensuring high performance while maintaining process simplicity
3Manufacturing precision
If multiple photolithography and ion implant steps are used to achieve precise dopant distributions, then component performance is optimized, but fabrication cost increases
Solution Approach 1:
The patent replaces the mechanical and chemical systems of photolithography and ion implantation with an additive manufacturing system that directly deposits semiconductor materials with controlled dopant content. This substitution maintains precise dopant distribution control through material composition management while eliminating the complex equipment and multiple process steps required by conventional methods, thereby reducing fabrication cost
Data Source
AI summary
A microelectronic device is formed by forming at least a portion of a substrate of the microelectronic device by one or more additive processes. The additive processes may be used to form semiconductor material of the substrate. The additive processes may also be used to form dielectric material structures or electrically conductive structures, such as metal structures, of the substrate. The additive processes are used to form structures of the substrate which would be costly or impractical to form using planar processes. In one aspect, the substrate may include multiple doped semiconductor elements, such as wells or buried layers, having different average doping densities, or depths below a component surface of the substrate. In another aspect, the substrate may include dielectric isolation structures with semiconductor material extending at least partway over and under the dielectric isolation structures. Other structures of the substrate are disclosed.