Additive Resistive Jumpers for Circuit Trimming
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Solution Overview
Problem
Existing methods for adjusting circuit performance parameters and configuring microelectronic devices during manufacturing, such as using fuses and EEPROMs, are costly, complex, and limit product flexibility and reliability due to the need for extra masking steps and precision programming procedures.
Innovation Solution
An additive deposition process is used to form conductive or resistive structures between exposed conductive routing structures on a processed wafer, allowing for the configuration of circuits and trimming of analog and digital circuits after wafer processing, without the need for additional masking layers or complex interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fuses, EEPROMs, or OTP memories are used for circuit trimming and configuration, then circuit performance parameters can be adjusted, but extra masking steps, more die area, and increased cost and complexity are required
Solution Approach 1:
The patent extracts the configuration function from traditional memory elements and fuses, replacing them with a dedicated resistive material deposition process. This separates the trimming function from complex memory structures, eliminating the need for EEPROM/OTP cells and their associated control logic, thereby reducing device complexity while maintaining circuit adjustment capability
Solution Approach 2:
The patent uses a simple resistive material layer that can be deposited and patterned once to establish permanent circuit configurations. This disposable-like approach replaces expensive, complex memory elements with a straightforward resistive structure that achieves the same trimming function without requiring sophisticated programming procedures or multiple masking steps
2Manufacturing precision
If fuses, EEPROMs, or OTP memories are used for circuit configuration, then circuit trimming is enabled, but extra masking steps and more die area are required
Solution Approach 1:
The patent extracts the trimming function from bulky memory elements and implements it through a thin resistive material layer deposited directly on the circuit. This reduces the area required for trimming from the size of EEPROM/OTP cells to a minimal resistive structure, significantly decreasing die area while preserving circuit trimming capability
Solution Approach 2:
The patent changes the physical state and properties of the resistive material through controlled deposition parameters (thickness, composition, pattern geometry) to achieve the desired resistance values for circuit trimming. This allows precise circuit adjustment without requiring large-area memory structures, as the resistance can be tuned by modifying deposition parameters rather than using extensive memory cell arrays
3Reliability
If traditional memory elements and fuses are used, then circuit configuration is possible, but precision special multiple pass test and programming procedures are required to ensure reliability
Solution Approach 1:
The patent employs a simple resistive material structure that can be deposited and patterned in a single straightforward process, eliminating the need for complex multi-pass programming procedures. The resistive structure serves its configuration purpose without requiring sophisticated test and programming equipment, thereby maintaining reliability while reducing procedural complexity
Solution Approach 2:
The patent replaces the complex mechanical and electrical programming procedures required for EEPROM/OTP with a straightforward material deposition and patterning process. This substitution of the configuration mechanism eliminates the need for precision special test and programming procedures, as the resistive structure is established through a single deposition step rather than multiple programming passes
4Adaptability or versatility
If fuses, EEPROMs, or OTP memories are used for circuit adjustment, then product flexibility is achieved, but cost and complexity increase
Solution Approach 1:
The patent extracts the configuration capability from expensive memory elements and implements it through a simple resistive material deposition process. This separation allows product flexibility to be achieved through a cost-effective manufacturing process that does not require complex memory structures, thereby maintaining adaptability while reducing manufacturing cost and complexity
Solution Approach 2:
The patent uses an inexpensive resistive material layer that can be deposited and patterned once to establish permanent circuit configurations. This approach replaces expensive memory elements with a cost-effective resistive structure, achieving product flexibility without the high manufacturing costs and complexity associated with EEPROM/OTP cells
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible and reliable configuration of microelectronic devices with reduced die area requirements, allowing for unique configuration of each die based on probe measurements, enhanced circuit reliability, and cost-effective manufacturing, while avoiding the limitations of traditional methods like polysilicon fuses.
Implementation Method 1
An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure
Data Source
AI summary
A first conductive routing structure is electrically connected to a first electronic component. A second conductive routing structure is electrically connected to a second electronic component. An additive deposition process deposits a material over a surface of a processed wafer to form a conductive or resistive structure, which extends from a portion of the first conductive routing structure to a portion of the second conductive routing structure, to configure a circuit including the first and second electronic components.