Additively Manufactured Interconnect for Wafer Testing
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Solution Overview
Problem
Wafer-level testing faces challenges in achieving high touchdown efficiency and minimizing electrical and mechanical interference between test circuitry of adjacent dice, due to the fragile nature of dice and the need for a good electrical path with low loss, low inductance, and low crosstalk, which complicates parallel testing.
Innovation Solution
An interconnect system comprising additively-manufactured electrical conduits with electrically-conductive material, surrounded by dielectric materials, and potentially a coaxial structure, is used to connect a circuit board with electrical elements at a first pitch to a wafer with contacts at a second pitch, less than the first pitch, ensuring matching electrical path lengths, impedances, and signal attenuation, and including mechanically-compliant contacts for efficient signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If dice are tested in a tight group to improve touchdown efficiency, then the ratio of actual touchdowns to theoretically necessary touchdowns increases, but electrical and mechanical interference between test circuitry of adjacent dice increases
Solution Approach 1:
The test wafer is divided into multiple independently testable regions or rings, where each region can be tested separately with its own test circuitry. This segmentation allows tight grouping of dice for efficient touchdowns while isolating the test circuitry of different groups to prevent electrical and mechanical interference between them.
2Reliability
If test circuitry is placed close to dice to achieve low loss and low inductance, then electrical path quality improves, but mechanical interference and crosstalk between adjacent test circuitry increases
Solution Approach 1:
Each test region on the wafer is equipped with dedicated test circuitry optimized for local testing needs, with electrical paths tailored to minimize loss and inductance for that specific region. The test circuitry density and configuration vary by location, allowing close placement where needed while maintaining signal integrity, and isolation where crosstalk would be problematic.
3Object-generated harmful factors
If dice are spread out on the wafer to reduce interference between test circuitry, then electrical and mechanical interference decreases, but touchdown efficiency decreases
Solution Approach 1:
Multiple levels of test organization are implemented, with dice nested within test regions, which are nested within larger wafer zones. This nested structure allows efficient grouping of dice at the regional level for high touchdown efficiency, while the hierarchical organization prevents interference between circuitry at different levels by providing natural isolation boundaries.
4Reliability
If a very short electrical path is implemented on the test board to achieve low loss and low inductance, then electrical path quality improves, but the area required for test circuitry per die increases
Solution Approach 1:
The test circuitry is distributed across the wafer surface in a two-dimensional arrangement rather than being concentrated in a single plane on a traditional test board. This spatial distribution allows short electrical paths to be achieved locally at each test region while the overall wafer structure provides the testing framework, effectively reducing the area requirement per die compared to conventional board-based approaches.
Data Source
AI summary
A system includes: a circuit board including electrical elements arranged at a first pitch; a wafer including contacts arranged at a second pitch, where the second pitch is less than the first pitch; and an interconnect including additively-manufactured electrical conduits that are part of an electrical pathway between the electrical elements and the contacts, where the additively-manufactured electrical conduits include electrically-conductive material.