Address Array Data Processing for Storage Devices

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Solution Overview

Problem

Current data processing systems, such as eMMC and SD cards, face challenges in achieving high random read and write speeds due to inefficiencies in data transmission and storage operations.

Innovation Solution

A method is introduced that utilizes a newly defined address array to improve data processing speed by efficiently transmitting and storing data across multiple storage regions, including error correction encoding and simultaneous programming of data, allowing for continuous data transfer and reduced operation times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data is transmitted and processed sequentially in traditional eMMC/SD card systems, then the system structure remains simple, but the random read and write speeds are limited

Engineering Contradiction:

Improverandom read and write speedVSAvoiddata processing structure

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The host controller pre-generates and transmits an address array containing multiple start addresses before data transfer begins. This preliminary action allows the memory card to prepare multiple data regions in advance, enabling parallel data retrieval and significantly improving random read/write speeds without requiring complex real-time address calculation during data transfer

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The data storage is divided into multiple independent data regions, each associated with a specific start address from the address array. This segmentation allows the memory card to independently access and process multiple data regions simultaneously, transforming sequential operations into parallel operations and thereby increasing overall data processing speed

Inventive Principle:

Principle #1Segmentation

2Productivity

If data transfer operations are performed sequentially, then the control logic remains simple, but the Input/Output Per Second (IOPS) rate is reduced

Engineering Contradiction:

ImproveIOPS rateVSAvoidcontrol logic

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The system maintains continuous useful action by overlapping data transfer with address processing. While data is being transferred from one region, the controller simultaneously processes addresses for the next data region, ensuring that no time is wasted between operations. This continuous operation maximizes the IOPS rate by eliminating idle periods in the data processing pipeline

Inventive Principle:

Principle #20Continuity of useful action

Solution Approach 2:

The memory card dynamically switches between different data regions based on the address array, adapting its access pattern to the specific data retrieval requirements. This dynamic address mapping allows the system to optimize data access paths in real-time, improving IOPS by selecting the most efficient access routes for each data operation

Inventive Principle:

Principle #15Dynamics

3Loss of time

If error correction and data programming are performed sequentially, then the processing steps remain simple, but the overall processing time increases

Engineering Contradiction:

Improveprocessing timeVSAvoidoperation sequence

Core Design Contradiction:

Loss of timeVSDevice complexity

Solution Approach 1:

Error correction code (ECC) processing is performed preliminarily on data before it is programmed to the final storage location. By completing error correction in advance during the data reception phase, the system eliminates the need for separate ECC processing steps during the programming phase, thereby reducing total processing time without compromising data integrity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system merges the error correction operation with the data reception and programming operations into a unified processing flow. Instead of treating these as separate sequential steps, the operations are combined and overlapped, where ECC processing occurs concurrently with data transfer and programming preparation, thus reducing overall processing time while maintaining operational simplicity

Inventive Principle:

Principle #5Merging (Combining)

Data Source

PatentUS9465544B2Method of processing data and system using the same

Publication Date: 2016.10.11 SAMSUNG ELECTRONICS CO LTD

AI summary

A host generates an address array including a header and each start address to perform a data processing operation, which may for example be 4 Kbytes of a random read operation or a random write operation, and transmits a generated address array to a data storage device through a data bus. The data storage device, in the case of a random read operation, outputs each data corresponding to the each start address to the host successively by using the address array. In the case of a random write operation, the data storage device receives each data corresponding to each start address from the host and stores it in a memory core.