Address Buffer for Pseudo SRAM with Clock-Adaptive Latching
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Solution Overview
Problem
Existing semiconductor memory apparatuses face technical limitations in implementing address buffering operations that can function regardless of whether a clock is input, as synchronous and asynchronous address buffers operate improperly when the clock is selectively used, particularly in Pseudo SRAM applications.
Innovation Solution
An address buffer system that includes an address input unit, a clock synchronizing unit, a synchronous address latch unit, a synchronous mode detecting unit, and an asynchronous address latch unit, which generate and manage latch input addresses and output addresses based on clock presence, enabling both synchronous and asynchronous buffering operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a synchronous address buffer is used, then address buffering can be performed when clock is input, but it cannot operate when clock is not input
Solution Approach 1:
The address buffer is designed to perform both synchronous address buffering (when clock is input) and asynchronous address buffering (when clock is not input) using the same hardware structure. The buffer automatically switches between synchronous and asynchronous modes based on clock presence, eliminating the need for separate buffer circuits for different operating conditions.
2Reliability
If an asynchronous address buffer is used, then address buffering can be performed when clock is not input, but it cannot operate properly when clock is input
Solution Approach 1:
The address buffer dynamically adjusts its operating mode based on the presence or absence of a clock signal. When clock is detected, the buffer operates in synchronous mode; when clock is absent, it automatically switches to asynchronous mode. This dynamic adaptation allows the same hardware to reliably perform address buffering under varying clock conditions.
3Reliability
If separate synchronous and asynchronous address buffers are used, then each can operate in its designated mode, but device complexity increases
Solution Approach 1:
Instead of using separate synchronous and asynchronous address buffer circuits, the invention implements a single unified address buffer that can operate in both synchronous and asynchronous modes. This multi-functional design reduces device complexity by eliminating redundant hardware while maintaining reliable address buffering operations in both operating conditions.
Data Source
AI summary
An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch input address and a clock. A synchronous address latch unit generates a synchronous output address from a command pulse signal and the second latch input address. A synchronous mode detecting unit determines whether a mode is a synchronous mode or not from a valid address signal and the clock to generate a synchronous mode signal. An asynchronous address latch unit generates an asynchronous output address from the synchronous mode signal, an address strobing signal, and the second latch input address.