Address Bus Control for Shared Memory Access
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Solution Overview
Problem
Existing methods for controlling access to shared memory areas by multiple processes are complex and costly, often requiring indirect access and separate memory management units to ensure data integrity, which can lead to waiting times and data loss.
Innovation Solution
A method where one process controls part of the address bus to influence which memory area another process accesses, using writable control registers to manage access to data packets, allowing simultaneous access without waiting times or data loss, applicable to both dual-ported and single-ported RAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If indirect access through separate memory management control units is used to ensure data consistency, then data integrity is maintained, but device complexity and cost increase
Solution Approach 1:
The patent extracts the memory management control unit from the system, eliminating the need for separate control hardware. Instead, the host CPU directly controls the address bus to manage memory access, simplifying the overall system architecture while maintaining data consistency through software-based control mechanisms
Solution Approach 2:
The system enables self-service by allowing the host CPU to directly manage memory access without external control units. The CPU uses control registers to set address bus signals, enabling it to autonomously control which process accesses which memory area, eliminating the need for separate memory management hardware
2Reliability
If one process blocks access by another process to ensure data consistency, then data integrity is maintained, but productivity decreases due to waiting times
Solution Approach 1:
The patent implements dynamic memory access control where the host CPU can change the address bus signals at any time to switch between different processes accessing different memory areas. This dynamic control eliminates static blocking mechanisms, allowing flexible and efficient memory sharing without forcing processes to wait
Solution Approach 2:
The host CPU performs preliminary actions by setting control registers with address bus signals before memory access conflicts occur. This proactive control prevents blocking situations by pre-configuring the address bus to direct access to appropriate memory areas, ensuring smooth process switching without waiting times
3Reliability
If separate memory blocks (IBF shadow, OBF shadow) are provided for each process to ensure data consistency, then data integrity is maintained, but chip area increases
Solution Approach 1:
The patent merges the separate memory blocks (IBF shadow, OBF shadow) into a single shared message memory. The host CPU controls access to this unified memory by dynamically setting address bus signals, eliminating the need for duplicate memory blocks while maintaining data consistency through centralized address control
Solution Approach 2:
The single message memory serves multiple functions and is accessible by multiple processes simultaneously. The host CPU makes the memory universal by controlling the address bus to direct different processes to access different areas of the same memory, replacing the need for process-specific separate memory blocks
Data Source
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AI summary
The invention relates to a method for controlling access to regions of a storage (1) comprising a plurality of processes (2). In order to allow a plurality of processes to access the latest stored data packets stored in the storage (1) without loss of data and without a waiting period, according to the invention a first (#1) of the processes (2) controls part of an address bus (3) with which another (#2) of the processes (2) accesses the storage (1), wherein due to the control of the part of the address bus (3) the first process (#1) influences which storage region is accessed by the other process (2).