Address-Based Cache Write Policy for Coherence and Traffic Control

Solution Overview

Problem

The write-back cache hierarchy faces issues with coherence and delayed updates, where data consistency across cache levels is compromised due to stale data and delayed propagation of updates, particularly in systems without coherency guarantees, and write-through caches incur excessive memory traffic.

Innovation Solution

A cache system with a memory attribute register that designates memory address ranges as either write-through or write-back, allowing writes to addresses marked as write-through to update all levels of the memory hierarchy, while writes to addresses marked as write-back only update the first cache level, ensuring data consistency and reducing memory traffic.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If write-back policy is used in cache hierarchy, then memory traffic is reduced, but data coherence and update timeliness deteriorate

Engineering Contradiction:

Improvememory trafficVSAvoiddata coherence

Core Design Contradiction:

Loss of energyVSReliability

Solution Approach 1:

The patent applies local quality by allowing different cache lines to have different write policies (write-back or write-through) based on their specific characteristics such as access patterns and data importance. This enables the system to optimize memory traffic for frequently accessed data while maintaining coherence for critical data, resolving the contradiction between reducing memory traffic and ensuring data coherence.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamic write policy selection where the cache controller can change the write policy for different cache lines based on runtime conditions such as access patterns, data volatility, and system state. This dynamic adaptation allows the system to switch between write-back and write-through policies as needed, optimizing both memory traffic and data coherence according to actual usage patterns.

Inventive Principle:

Principle #15Dynamics

2Reliability

If write-through policy is used in cache hierarchy, then data coherence is maintained, but memory traffic increases excessively

Engineering Contradiction:

Improvedata coherenceVSAvoidmemory traffic

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by allowing different cache lines to have different write policies (write-back or write-through) based on their specific characteristics such as access patterns and data importance. This enables the system to optimize memory traffic for frequently accessed data while maintaining coherence for critical data, resolving the contradiction between reducing memory traffic and ensuring data coherence.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamic write policy selection where the cache controller can change the write policy for different cache lines based on runtime conditions such as access patterns, data volatility, and system state. This dynamic adaptation allows the system to switch between write-back and write-through policies as needed, optimizing both memory traffic and data coherence according to actual usage patterns.

Inventive Principle:

Principle #15Dynamics

3Loss of energy

If uniform write-back policy is applied to all cache lines, then memory traffic is minimized, but delayed updates and stale data propagate through the hierarchy

Engineering Contradiction:

Improvememory trafficVSAvoidupdate propagation time

Core Design Contradiction:

Loss of energyVSLoss of time

Solution Approach 1:

The patent applies local quality by allowing different cache lines to have different write policies (write-back or write-through) based on their specific characteristics such as access patterns and data importance. This enables the system to optimize memory traffic for frequently accessed data while maintaining coherence for critical data, resolving the contradiction between reducing memory traffic and ensuring data coherence.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent implements dynamic write policy selection where the cache controller can change the write policy for different cache lines based on runtime conditions such as access patterns, data volatility, and system state. This dynamic adaptation allows the system to switch between write-back and write-through policies as needed, optimizing both memory traffic and data coherence according to actual usage patterns.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9575901B2Programmable address-based write-through cache control

Publication Date: 2017.02.21 TEXAS INSTRUMENTS INC

AI summary

This invention is a cache system with a memory attribute register having plural entries. Each entry stores a write-through or a write-back indication for a corresponding memory address range. On a write to cached data the cache the cache consults the memory attribute register for the corresponding address range. Writes to addresses in regions marked as write-through always update all levels of the memory hierarchy. Writes to addresses in regions marked as write-back update only the first cache level that can service the write. The memory attribute register is preferably a memory mapped control register writable by the central processing unit.