Address Comparison Circuit Verification for Automotive Safety
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Solution Overview
Problem
Existing address comparison circuits in processing systems, such as those used in automotive electronics, face challenges in verifying their correct operation, particularly in ensuring proper address protection and fault coverage, which is critical for safety-critical applications like ISO26262 specifications.
Innovation Solution
A processing system with an address comparison circuit comprising iterative digital comparators to compare address values with upper and lower address limits, and a test circuit to verify the correct operation of these comparators, allowing for efficient testing and reduced test time and area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional address comparison circuits are used without dedicated test circuits, then device complexity is reduced, but reliability and fault coverage are insufficient for safety-critical applications
Solution Approach 1:
The test circuit is nested within the address comparison circuit structure, utilizing the same comparator units and address bus infrastructure. The test circuit injects test addresses through the existing address comparison logic, allowing verification of address protection functionality without adding completely separate testing infrastructure.
Solution Approach 2:
The address comparison circuit performs self-verification by using its own internal resources (comparators, address bus) to test its functionality. The test circuit leverages the existing comparison logic to validate address matching behavior, eliminating the need for external testing equipment or separate verification circuits.
2Measurement precision
If comprehensive testing of address comparison circuits is implemented, then measurement precision and fault detection capability are improved, but test time and area overhead increase
Solution Approach 1:
The test circuit pre-configures test addresses and limit values before executing comparisons. By preparing test data in advance and using systematic address sequences, the testing process efficiently covers all critical address matching scenarios without requiring extensive trial-and-error testing.
Solution Approach 2:
The test circuit varies address parameters (test address, upper limit, lower limit) systematically to validate different comparison scenarios. By changing these parameters in a structured manner, the test circuit comprehensively verifies address protection functionality while minimizing the number of test iterations required.
Data Source
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AI summary
A processing system (10a) comprising an address comparison circuit (40a) is described. The address comparison circuit (40a) is configured to compare an address value (IA) with an upper address limit (TAH) and a lower address limit (TAL). Specifically, for this purpose, a first iterative digital comparator (400) generates an upper-limit comparison signal (HH), a second iterative digital comparator (402) generates a lower-limit comparison signal (LH) and a combinational logic circuit (404) generates a combined comparison signal (RH). In particular, a test circuit (42) sets the address value (IA), the upper address limit (TAH) and the lower address limit (TAL) to a given reference bit sequence and verifies whether the upper-limit comparison signal (HH) and/or the lower-limit comparison signal (LH) have the correct values. Moreover, the test circuit repeats various operations for each of the bits of the address value (IA). Specifically, the test circuit sets (5006) the respective bit of the address value (IA) to high and sets the respective bit of the upper address limit (TAH) and the lower address limit (TAL) to low. Next, the test circuit verifies (5006) whether the upper-limit comparison signal (HH) is de-asserted and/or whether the lower-limit comparison signal (LH) is asserted. Moreover, the test circuit sets (5010) the respective bit of the address value (IA) to low, and sets the respective bit of the upper address limit (TAH) and the lower address limit (TAL) to high. Next, the test circuit verifies (5012) whether the upper-limit comparison signal (HH) is asserted and/or whether the lower-limit comparison signal (LH) is de-asserted. Finally, the test circuit sets (5014) the respective bit of the address value (IA), the upper address limit (TAH) and the lower address limit (TAL) again to the same logic level (0_1).