Address Compression Using Reverse Map Cache for Low-Latency Memory Access
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Solution Overview
Problem
The combination of compressed addressing (CA) and dynamic segment allocation (DSA) in JavaScript engines leads to increased memory access latency, making it difficult to allocate memory for lightweight JavaScript engines and external libraries on microcontrollers, especially for applications like DNN-based machine learning or IoT standard communication.
Innovation Solution
A method and apparatus for compressing addresses using a reverse map cache (RMC) and reverse map tree (RMT) to reduce memory access by converting full-bitwidth addresses into low-bitwidth addresses, thereby minimizing latency and memory usage, allowing for a resizable JavaScript heap that can accommodate both JavaScript applications and external libraries on microcontrollers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic segment allocation (DSA) and compressed addressing (CA) are used together, then memory space can be allocated for both JavaScript engine and external libraries, but memory access latency greatly increases
Solution Approach 1:
The patent pre-allocates a fixed-size reverse map cache (RMC) structure at the beginning to store segment base addresses. This preliminary action allows subsequent address compression operations to quickly check the RMC without performing full reverse map searches, thereby reducing memory access latency while maintaining the adaptability benefits of dynamic segment allocation
Solution Approach 2:
The patent segments the address space into fixed-size segments and uses the RMC to store only the base addresses of these segments. This segmentation approach allows the system to handle large memory spaces efficiently by breaking them into manageable segments, reducing the complexity of address translation while maintaining flexible memory allocation
2Productivity
If full-bitwidth addresses are used without compression, then address translation is simple, but memory usage increases and latency increases in dynamic segment allocation
Solution Approach 1:
The patent implements partial address compression by only translating the necessary portions of addresses through the RMC lookup process. Instead of fully compressing all address components, the system performs selective translation based on RMC hits, reducing the overhead of address compression while still achieving memory efficiency benefits
Solution Approach 2:
The patent creates a simplified copy of the reverse map information in the RMC structure, storing only the essential segment base address mappings. This copied information allows quick lookup without accessing the full reverse map data structures, reducing address translation latency while maintaining memory efficiency
Data Source
AI summary
A method of compressing an address includes receiving an input of a full address including a first part and a second part; checking a segment base address based on the first part in a previously stored reverse map cache (RMC); obtaining a block offset based on the segment base address and the second part; and outputting a compressed address by compressing the first part and the second part, respectively, based on the segment base address and the block offset.