Address Control Circuit for Semiconductor Memory Refresh Testing
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Solution Overview
Problem
Semiconductor memory apparatuses face challenges in maintaining data integrity during refresh operations, as self-refresh addresses cannot be externally changed or monitored, making it difficult to diagnose failures during these operations.
Innovation Solution
An address control circuit is designed with a data mask buffer, decoder, and latch block to generate and latch test refresh addresses, allowing for external testing and diagnosis of refresh operations by decoding data mask information and selectively latching normal or test refresh addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If self-refresh operation is performed internally without external commands, then the semiconductor memory apparatus can maintain data automatically, but the refresh addresses cannot be externally changed or monitored making failure diagnosis difficult
Solution Approach 1:
The patent introduces a test mode signal as an intermediary that mediates between the internal self-refresh operation and external testing requirements. When the test mode signal is activated, it enables the data mask buffer to receive external coded refresh addresses and the latch block to output these addresses externally, allowing monitoring without disrupting the fundamental self-refresh mechanism. This intermediary signal resolves the contradiction by enabling external observation only when needed while maintaining internal autonomous operation during normal use.
Solution Approach 2:
The patent changes the operational parameters of the address control circuit by introducing a test mode parameter that switches the circuit between normal self-refresh mode and test mode. In test mode, the circuit parameters are adjusted to allow external address input through the data mask buffer and external address output through the latch block, while in normal mode, the circuit operates with internal counter-generated addresses only. This parameter change enables the system to adapt between reliability-oriented autonomous operation and diagnostics-oriented external monitoring.
2Loss of energy
If the address buffer stops operating during refresh operation to reduce current, then current consumption is minimized, but the ability to input external addresses during refresh is lost
Solution Approach 1:
The patent makes the address buffer's operational state dynamic by controlling its activation through the test mode signal. During normal refresh operations, the address buffer remains inactive to minimize current consumption. However, when the test mode signal is activated, the address buffer becomes dynamically active, allowing external coded refresh addresses to be input through the data mask buffer. This dynamic state change enables the system to optimize power consumption during normal operation while providing external address input capability when testing is required.
Data Source
AI summary
An address control circuit for a semiconductor memory apparatus so as to make a refresh operation test possible by designating a refresh address is presented. The circuit includes a buffer block, a decoder, and a latch block. The buffer block receives coding information coded testing address information in accordance to a test signal. The decoder generates a test refresh address by decoding the coding information. The latch block latches the test refresh address depending on the test signal.