Address Conversion Using Fake Buffers for SoC Memory Reduction
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Solution Overview
Problem
Data transmission between components on a SOC (System on a Chip) requires two buffers, leading to resource wastage and consumption in the memory.
Innovation Solution
An address conversion system utilizing a real buffer and a fake buffer, coupled through a memory bus coupler, to facilitate data transmission between components with different addresses without increasing hardware resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two different components are equipped with two buffers for data transmission, then data transmission between components with different addresses is achieved, but memory resources are consumed and wasted
Solution Approach 1:
The patent creates a fake buffer that copies the address space of the real buffer without actually allocating physical memory resources. The fake buffer algorithm generates virtual addresses that map to the real buffer, allowing components to access data as if separate buffers existed while actually sharing a single physical buffer, thus reducing memory consumption while maintaining transmission capability
Solution Approach 2:
The single real buffer serves multiple functions by being shared between different components through address translation. Instead of requiring dedicated buffers for each component pair, the real buffer is universally accessed by multiple components via the coupler's address conversion, making one buffer serve the role of multiple buffers and reducing overall memory resource requirements
2Quantity of substance
If address conversion is implemented to share a single buffer between components, then memory resource consumption is reduced, but system complexity increases due to coupler and address translation mechanisms
Solution Approach 1:
The coupler acts as an intermediary between components with different address spaces and the shared real buffer. It handles address translation and data routing, mediating access between the fake buffer addresses used by components and the real buffer's physical addresses, thereby enabling resource sharing while managing the complexity of address conversion through a dedicated intermediary component
Solution Approach 2:
The patent replaces the mechanical approach of providing separate physical buffers for each component with a software-based address translation mechanism. The fake buffer algorithm and coupler use logical address mapping instead of physical duplication, substituting hardware resource allocation with software-managed virtual addressing, which reduces physical complexity while enabling resource sharing
Data Source
AI summary
The address conversion system includes a storage device, a memory bus, and a processor. The processor is configured to execute the following steps: generating a real buffer on the storage device; generating a fake buffer in a fake capacity of the storage device by a fake buffer algorithm; establishing a coupling relationship between the real buffer and the fake buffer through a coupling algorithm by the coupler of the memory bus; receiving a compressed data from a first device by the real buffer; when a second device wants to read the fake buffer, the coupler guides the second device to the real buffer through the coupling relationship for reading; transmitting the compressed data of the real buffer to the coupler by the memory bus; decompressing the compressed data into a decompressed data by the coupler; and transmitting the decompressed data to the second device by the memory bus.