Address Conversion Circuit for Shared Boot Memory in Data Processing
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Solution Overview
Problem
In data processing systems with SIMD processors, the host CPU bears a significant load and incurs increased costs due to the need for separate boot memories, interfaces, and development environments, complicating programming and management, especially when coordinating with SIMD processors.
Innovation Solution
A data processing apparatus is designed with a second CPU that controls the SIMD processor via an arithmetic unit bus, sharing external memory and boot memory, and utilizing an address conversion unit to manage different addresses for each processor, reducing the host CPU's load and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a host CPU controls the entire system including SIMD processor, then the system can operate, but the host CPU bears significant load and programming becomes complicated
Solution Approach 1:
The control function is segmented between the host CPU and a dedicated control CPU. The control CPU specifically manages the SIMD processor while the host CPU handles other system operations, dividing the control burden and simplifying programming for each processor.
Solution Approach 2:
A control CPU acts as an intermediary between the host CPU and SIMD processor. This intermediate controller handles the coordination and control signals, reducing the direct control load on the host CPU and simplifying the interface complexity.
2Reliability
If separate boot memories are prepared for host CPU and control CPU, then each processor can boot independently, but the number of I/O terminals and cost increase
Solution Approach 1:
The boot memories for the host CPU and control CPU are merged into a single shared boot memory. The address conversion circuit enables both processors to access different regions of the same memory, reducing the number of I/O terminals while maintaining independent boot capability.
Solution Approach 2:
A single boot memory serves multiple functions by being shared between the host CPU and control CPU. Through address conversion, the same physical memory resource fulfills the boot requirements of both processors, demonstrating multi-functionality.
3Device complexity
If address conversion is implemented to share boot memory, then memory sharing is achieved, but address management becomes complex in data processing
Solution Approach 1:
The address conversion is applied locally only to boot memory access, while data memory access uses direct addresses. This localized application of address conversion simplifies address management in data processing while still achieving boot memory sharing.
4Productivity
If a dedicated control CPU is added to control SIMD processor, then host CPU load is reduced and performance improves, but system cost and package countermeasure cost increase
Solution Approach 1:
Multiple system resources (boot memory, data memory, I/O terminals) are merged and shared between the host CPU and control CPU. This consolidation reduces the overall package size and countermeasure costs while maintaining the performance benefits of having a dedicated control CPU.
Solution Approach 2:
The control CPU and associated resources are designed to serve multiple functions: controlling the SIMD processor, sharing boot memory, and potentially coordinating with the host CPU. This multi-functionality justifies the added component by providing multiple benefits rather than a single function.
Data Source
AI summary
The present invention provides a data processing apparatus realizing reduced load on a host CPU and improved performance. An arithmetic unit includes an SIMD processor for processing a plurality of pieces of data by a single instruction, and a second CPU coupled to the SIMD processor via an arithmetic unit bus and controlling the SIMD processor. A host system includes a host CPU for controlling the entire data processing apparatus, a built-in memory and a peripheral circuit coupled to the host CPU via a first bus, and a peripheral circuit coupled to a second bus. The second CPU accesses an external flash/ROM via the arithmetic unit bus and the first bus, and the SIMD processor accesses an external memory via the second bus. Therefore, the load on the host CPU can be reduced, and the performance of the entire apparatus can be improved.