Address Conversion Table Caching in Storage Controllers
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Solution Overview
Problem
The existing storage devices face inefficiencies in managing address conversion tables, as caching them in volatile memory reduces the available space for other purposes and requires complex data arrangement strategies to optimize storage capacity.
Innovation Solution
A storage device configuration that includes a nonvolatile memory and a volatile memory, with a controller managing the address conversion table by writing data in different formats to optimize storage efficiency, allowing for reduced size storage of the address conversion table in volatile memory by using regions and ECC frames, and efficiently handling data alignment and offset processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the address conversion table is cached in volatile memory, then access speed is improved, but the available space for other purposes decreases
Solution Approach 1:
The address conversion table is divided into multiple regions (first region, second region, third region) with different storage requirements. The first region stores frequently accessed entries in volatile memory for high-speed access, while the second and third regions store less frequently accessed entries in non-volatile memory, segmenting the table to optimize both speed and space utilization.
Solution Approach 2:
Different parts of the address conversion table are stored with different qualities - the first region uses volatile memory for high-speed access to frequently accessed entries, while the second and third regions use non-volatile memory for persistent storage of less frequently accessed entries, applying local quality optimization to each segment.
2Reliability
If the address conversion table is stored in nonvolatile memory, then data persistence is improved, but access speed decreases
Solution Approach 1:
The address conversion table is segmented into volatile and non-volatile storage portions. The first region in volatile memory provides fast access for frequently used entries, while the second and third regions in non-volatile memory ensure data persistence, resolving the contradiction between speed and reliability through segmentation.
Solution Approach 2:
Volatile memory acts as an intermediary between the non-volatile memory storage and the CPU. Frequently accessed address conversion entries are loaded into volatile memory from non-volatile memory, creating a fast-access cache layer that maintains data persistence while improving access speed through the intermediary volatile memory layer.
3Quantity of substance
If complex data arrangement strategies are used to optimize storage capacity, then storage efficiency is improved, but device complexity increases
Solution Approach 1:
The address conversion table is divided into three distinct regions with clear purposes: first region for high-speed volatile storage, second region for persistent non-volatile storage, and third region for additional persistent storage. This segmentation simplifies the data arrangement strategy by creating distinct, easily manageable zones rather than complex intermixed structures.
Solution Approach 2:
The system dynamically manages the first region by loading and unloading data between volatile and non-volatile memory based on access patterns, while maintaining the second and third regions as static persistent storage. This dynamic approach to only the necessary region optimizes storage capacity without requiring complex arrangements across the entire structure.
Data Source
AI summary
A storage device includes a nonvolatile memory, a volatile memory, and a controller accesses the nonvolatile memory using an address conversion table including regions, each region including entries, each entry storing a physical address of the nonvolatile memory in association with a logical address, and reads and writes data of the address conversion table from and to the nonvolatile memory and the volatile memory in a unit of a frame. The controller writes, to the nonvolatile memory, data of a first region in a first format in which a head address of data of a region aligns with a head address of a frame, and writes, to the volatile memory, data of a second region in either the first format or a second format in which a head address of data of a region does not align with a head address of a frame.