Address Converter Segments 64-bit AXI Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor device architectures like AXI, the fixed 64-bit address range is not fully available for accessing a host when used to access multiple slave regions, limiting the effective address range to 63 bits or less, which is undesirable, especially in applications like NVMe where full 64-bit addressing is necessary.
Innovation Solution
An apparatus and method that disassemble a full n-bit address into an m-bit upper address portion and an (n−m)-bit lower address portion, where the upper portion is sent via a sideband path and the lower portion via a main path, allowing the full address range to be reconstructed and made available to the host, using address converters integrated on a semiconductor die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the AXI switch uses the most significant bit (MSB) AXI address portion for decoding slave regions, then each AXI slave region can be addressed, but the effective address range for the host is reduced to 63 bits or less
Solution Approach 1:
The patent segments the 64-bit address into two parts: the first 6 bits are used for slave region decoding in the AXI switch, while the remaining 58 bits are preserved for host addressing. This segmentation allows both slave region access and full host address space to coexist without conflict.
Solution Approach 2:
The patent introduces an address converter as an intermediary component between the AXI master and the AXI switch. This converter translates the full 64-bit host address into a format suitable for the AXI switch's slave region decoding while preserving the ability to reconstruct the full address for the host.
2Adaptability or versatility
If more AXI slave regions are added to the switch, then more devices can be accessed, but fewer address bits remain available for the host
Solution Approach 1:
The patent establishes a clear segmentation where the first 6 bits of the address are dedicated to slave region selection, allowing up to 64 slave regions to be addressed. The remaining 58 bits are exclusively available for host addressing, ensuring that adding more slave regions does not reduce the host address space.
3Ease of operation
If the fixed 64-bit address range is used for AXI slave regions, then slave access is enabled, but full 64-bit addressing to the host is not available
Solution Approach 1:
The address converter serves as a mediator that translates between the AXI protocol's fixed address format and the host's full 64-bit addressing requirements. It preserves the ease of slave access while enabling full host address range.
Solution Approach 2:
The patent changes the address parameter handling by using the first 6 bits for slave region decoding and preserving the remaining bits for host addressing. This parameter separation allows both slave access and full host addressing to coexist.
Data Source
AI summary
An apparatus includes a first address converter coupled to a first device and a second device and configured to convert a first n-bit address received from the first device into an m-bit upper address portion and an (n−m)-bit lower address portion and forward the m-bit upper address through a side path and the (n−m)-bit lower address portion through a main path to the second device, m and n are positive integers, and a second address converter configured to assemble the m-bit upper address portion and the (n−m)-bit lower address portion to a second n-bit address that is a representation of the first n-bit address and provide the second n-bit address to a third device.