Address Converting Circuit for Sequential Bank Access
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing data access across multiple banks, particularly in sequencing data input/output operations, which affects performance and efficiency.
Innovation Solution
An address converting circuit with an address latch unit and a variable address generation unit is introduced, allowing for sequential data input/output by generating latch addresses and variable addresses to prioritize and manage data access paths between bank groups, enabling flexible sequencing of data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data access operations are performed simultaneously across multiple banks using the same address, then data output speed is improved, but control complexity of the data access path increases
Solution Approach 1:
The patent segments the bank selection process by dividing banks into different groups (first bank group and second bank group) with predetermined access priorities. The address converting circuit segments the address decoding process into two stages: first decoding to select bank groups, then selecting specific banks within groups. This segmentation allows simultaneous access across multiple banks while maintaining controlled complexity through hierarchical management.
Solution Approach 2:
The patent applies preliminary action by pre-establishing access priority sequences for different bank groups before data access operations begin. The address converting circuit uses predetermined priority information to automatically determine which bank group should be accessed first, eliminating the need for complex real-time arbitration logic during data access operations.
2Reliability
If sequential data input/output is implemented according to bank sequence, then data access control is improved, but access time increases
Solution Approach 1:
The patent implements dynamic bank group selection based on the current access state. The address converting circuit dynamically determines which bank group to access next by combining the decoded address with predetermined priority information and current access status. This dynamic approach maintains reliable sequential control while minimizing access time by automatically selecting the optimal bank group based on real-time conditions.
Solution Approach 2:
The patent uses feedback mechanisms where the address converting circuit monitors the access state of each bank group and uses this information to determine subsequent access sequences. The circuit feeds back the current access status to the address decoding logic, enabling intelligent sequential control that adapts to the actual state of the memory system, thereby maintaining reliability while reducing unnecessary access delays.
3Productivity
If multiple bank groups are accessed with the same address simultaneously, then data throughput is improved, but address decoding complexity increases
Solution Approach 1:
The patent segments the address space into different bank group ranges, with each bank group assigned to a specific address range. The address converting circuit segments the decoding process into two independent stages: first stage decodes the upper address bits to select bank groups, second stage decodes lower bits to select specific banks within groups. This segmentation enables simultaneous access to multiple bank groups using the same address pattern while keeping decoding complexity manageable through modular design.
Solution Approach 2:
The address converting circuit implements universal address decoding that can simultaneously handle multiple bank groups. The same decoded address can be applied to multiple bank groups in parallel, allowing the circuit to serve multiple functions: selecting bank groups, selecting banks within groups, and managing access priorities all through a unified decoding mechanism, thereby improving throughput without proportionally increasing complexity.
Data Source
AI summary
A semiconductor memory includes an address converting circuit which latches an address and a bank signal and generates a latch address for activating a data access path of a second bank group, and converts the latch address according to a level of the bank signal and generates a variable address for activating a data access path of a first bank group, a first column decoder which decodes the variable address and generates a first output enable signal for activating the data access path of the first bank group, and a second column decoder which decodes the latch address and generates a second output enable signal for activating the data access path of the second bank group.