Address Decoder Circuit for Bipolar Resistive RAM
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Solution Overview
Problem
Conventional two-transistor decoder circuits in memory systems are inefficient in delivering current in both directions for bi-polar resistive RAM, requiring additional transistors and wires to improve current efficiency, which increases complexity and space, undesirable in compact applications.
Innovation Solution
An address decoder circuit with select lines and a polarity line that switches the coupling of access lines between two select lines based on address information and polarity signals, using PFET and NFET transistors to efficiently handle voltage and current flow in different directions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional two-transistor decoder circuits are used, then circuit simplicity is maintained, but current efficiency in both directions for bi-polar resistive RAM is poor
Solution Approach 1:
The patent implements dynamic switching of select line coupling based on operation phase and polarity. The decoder circuit switches between coupling the access line to the first select line during first phases and to the second select line during second phases, allowing current to flow efficiently in both directions through the memory cell without requiring additional transistors for bidirectional control
2Reliability
If additional PFET and NFET transistors are added to form CMOS transmission gates, then current efficiency improves, but circuit area and wire count increase
Solution Approach 1:
The patent makes the existing NFET transistor perform multiple functions: it acts as a pass transistor during first phases and as part of a transmission gate during second phases. The same transistor structure serves different purposes in different operation phases, eliminating the need for additional dedicated transistors for bidirectional current flow
Solution Approach 2:
The patent uses periodic switching between two operation phases to achieve bidirectional current flow. During first phases, current flows in one direction with the access line coupled to the first select line; during second phases, current flows in the opposite direction with the access line coupled to the second select line. This time-multiplexed approach achieves full bidirectional functionality without additional hardware
3Reliability
If additional NFET transistor is placed in parallel with PFET transistor, then current efficiency improves, but wire count and circuit complexity increase
Solution Approach 1:
The patent dynamically reconfigures the circuit topology by switching which select line is coupled to the access line based on the operation phase. This dynamic reconfiguration allows the same physical wires to serve different functional purposes, achieving the effect of having additional current paths without actually adding more wires
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the number of components and space required, enabling efficient current flow in both directions without the need for additional transistors and wires, enhancing circuit compactness and simplicity.
Implementation Method 1
NFET transistors may be advantageous for delivering low voltages
Implementation Method 2
PFET transistors may be advantageous for delivering high voltages
Data Source
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Figure 3(1)
AI summary
Apparatuses, memories, and methods for decoding memory addresses for selecting access lines in a memory are disclosed. An example apparatus includes an address decoder circuit coupled to first and second select lines, a polarity line, and an access line. The first select line is configured to provide a first voltage, the second select line is configured to provide a second voltage, and the polarity line is configured to provide a polarity signal. The address decoder circuit is configured to receive address information and further configured to couple the access line to the first select line responsive to the address information having a combination of logic levels and the polarity signal having a first logic level and further configured to couple the access line to the second select line responsive to the address information having the combination of logic levels and the polarity signal having a second logic level.