Address Decoder Failure Detection Circuitry
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Solution Overview
Problem
Automotive data storage devices often fail to properly decode (x+y)-bit addresses, leading to incorrect access of memory cells, which can result in catastrophic failures, especially in systems like advanced engine control, due to the inability to accurately provide wordlines and bitlines.
Innovation Solution
The data storage device includes a row decoder and column decoder that compare subsets of wordlines and bitlines to detect failures in decoding x-bit row and y-bit column addresses, using parallel address decoders and failure detection circuitry to determine if the decoding has resulted in incorrect access by identifying differences in control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the data storage device uses a standard address decoder to decode (x+y)-bit addresses, then the device complexity is reduced, but the reliability of address decoding fails because the decoder cannot properly decode addresses, leading to incorrect memory cell access
Solution Approach 1:
The address decoding function is segmented into multiple parallel address decoders, each handling a portion of the address space. Each decoder independently decodes a subset of addresses and activates corresponding wordlines or bitlines. This segmentation allows the system to detect decoding failures by comparing outputs from multiple decoders while maintaining manageable complexity in each individual decoder unit.
Solution Approach 2:
The system implements feedback through comparison circuitry that monitors the outputs of multiple parallel address decoders. The comparison results are fed back to detect discrepancies in decoding, allowing the system to identify when a decoder fails to properly decode an address. This feedback mechanism enhances reliability without requiring complete redesign of the decoder architecture.
2Reliability
If the data storage device implements failure detection circuitry with parallel address decoders, then the reliability of address decoding is improved, but the device complexity increases due to additional comparators and control logic
Solution Approach 1:
The system performs preliminary decoding actions by having multiple parallel address decoders simultaneously decode the same address before the final selection is made. This preliminary action allows the comparison circuitry to detect potential failures before they result in incorrect memory access, enhancing reliability without adding complex post-decoding verification logic.
Solution Approach 2:
The system creates copies of the address decoding function through multiple parallel decoders. Each decoder is a copy of the basic decoding logic, and their outputs are compared to ensure consistency. This copying approach allows failure detection through simple comparison of identical structures, avoiding the need for complex verification circuitry while maintaining high reliability.
3Measurement precision
If the data storage device compares outputs from multiple parallel address decoders, then the measurement precision of address decoding is improved, but the loss of time increases due to additional comparison operations
Solution Approach 1:
The comparison operation is performed periodically as part of the normal address decoding process, rather than as a separate verification step. The parallel decoders operate simultaneously, and their outputs are compared in the same clock cycle as the decoding occurs. This periodic integration ensures high measurement precision without adding significant time overhead, as the comparison is embedded in the regular decoding rhythm.
Solution Approach 2:
The address decoding and output comparison functions are merged into a single integrated process. Multiple parallel decoders perform decoding and comparison operations simultaneously, combining what would otherwise be sequential operations into parallel execution. This merging reduces the total time required, as the comparison does not wait for decoding to complete but occurs concurrently, maintaining high accuracy without time penalty.
Data Source
AI summary
A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.