Address Decoder Open Fault Detection Using Single-Bit Derived Addresses
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Solution Overview
Problem
Existing techniques for detecting address decoder open faults in memory devices are inefficient, requiring extensive testing time and multiple commands, and struggle to generate appropriate address sequences for all configurations, especially when the ratio of subaddress decoder width to overall address width is high.
Innovation Solution
A test sequence apparatus that generates a series of derived addresses differing from a base address by a single bit, using base address generation circuitry and derived address generation circuitry, including a shift register, to automatically detect address decoder open faults, applicable to any memory configuration and ratio of subaddress decoder width to overall address width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single step test with specified test commands is used to detect address decoder open faults, then the test can be performed with clear control, but the testing time becomes very large and multiple commands are required
Solution Approach 1:
The patent pre-generates complete address sequences using LFSR circuits before testing begins. The address sequences are stored in buffers and automatically fed to the memory device during testing, eliminating the need for multiple test commands to be issued during the actual test execution. This preliminary preparation of test data resolves the contradiction by enabling continuous automated testing without command overhead.
Solution Approach 2:
The test system uses self-generated address sequences from LFSR circuits and automatic comparison logic to detect faults without requiring external controller intervention for each test step. The system autonomously generates addresses, performs writes, reads back data, and detects faults, reducing testing time by eliminating repeated command issuances while maintaining detection precision.
2Extent of automation
If LFSR-based address sequence generation is used to automate testing, then testing can be more automated, but different LFSR configurations are required for different address width ratios and no solution exists for certain configurations
Solution Approach 1:
The patent employs a unified LFSR-based address sequence generation approach that works across all address width ratios and memory configurations. Rather than designing separate LFSR configurations for different cases (as in prior art), this invention uses a single universal generation method that adapts to any configuration, resolving the contradiction between automation and adaptability.
Solution Approach 2:
The invention changes the parameters of the LFSR (such as feedback coefficients and initial states) dynamically based on the specific memory configuration being tested. This allows the same LFSR circuit structure to generate appropriate address sequences for different address width ratios and memory types, achieving both high automation and universal adaptability across all configurations.
Data Source
AI summary
The apparatus comprises derived address generation circuitry, responsive to a base address portion of each base address, to generate an associated series of derived addresses. Each derived address is different from other derived addresses in that associated series and has a derived address portion that differs from the corresponding base address portion by a single address bit value. Read/write sequence generator circuitry is then responsive to each base address in turn, to write in said memory device a first data value at the base address and a second data value at each derived address in the associated series of derived addresses and is arranged to read a data value stored at the base address each time the second data value is written to one of the derived addresses, and to detect an address decoder open fault if the read data value is the second data value.