Address Decoder Gate Leakage Reduction via Segmented MOS Control

Solution Overview

Problem

As semiconductor memory devices integrate more densely, the increasing number of row and column decoders leads to higher leakage currents in MOS transistors, significantly increasing power consumption, making high power-consumption devices unsuitable for small-sized or portable systems.

Innovation Solution

An address decoder is designed to reduce gate leakage current by isolating the gate input of MOS transistors through a pre-decoder that divides column addresses into groups and generates both a first and an inverted pre-decoding signal group, allowing the column decoder to operate MOS transistors at different voltage levels, thereby controlling column selection signals effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the number of row decoders and column decoders is increased to match higher integration degree, then the decoding capability and integration degree are improved, but the leakage current and power consumption increase significantly

Engineering Contradiction:

Improveintegration degreeVSAvoidpower consumption

Core Design Contradiction:

ProductivityVSLoss of energy

Solution Approach 1:

The patent segments the gate control into two independent parts: a first gate terminal controlled by a first control signal and a second gate terminal controlled by a second control signal. This segmentation allows independent optimization of each gate's control, enabling the first gate to be optimized for drive strength while the second gate is optimized for leakage reduction, thereby resolving the contradiction between integration degree and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different control signals to different gate terminals of the same MOS transistor, creating local quality differences in gate control. The first gate terminal receives a control signal optimized for its specific function (e.g., drive strength), while the second gate terminal receives a control signal optimized for leakage reduction. This local differentiation allows each gate to operate at its optimal point, reducing overall power consumption while maintaining high integration capability.

Inventive Principle:

Principle #3Local quality

2Loss of energy

If the gate width of MOS transistors is reduced to minimize leakage current, then the power consumption is reduced, but the drive strength and switching performance deteriorate

Engineering Contradiction:

Improveleakage currentVSAvoiddrive strength

Core Design Contradiction:

Loss of energyVSPower

Solution Approach 1:

The patent segments the gate control into two independent parts: a first gate terminal controlled by a first control signal and a second gate terminal controlled by a second control signal. This segmentation allows independent optimization of each gate's control, enabling the first gate to be optimized for drive strength while the second gate is optimized for leakage reduction, thereby resolving the contradiction between integration degree and power consumption.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent dynamically controls the two gate terminals with different control signals that can be adjusted independently. This dynamic control allows the system to adapt the gate widths and drive strengths in real-time based on operational requirements, optimizing the balance between leakage current and drive strength for different working conditions.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10410702B2Address decoder and semiconductor memory device including the same

Publication Date: 2019.09.10 SK HYNIX INC

AI summary

An address decoder and a semiconductor memory device including the same are disclosed, which relate to a technology for a decoding circuit configured to decode a column address. The address decoder includes a pre-decoder and a column decoder. The pre-decoder divides a plurality of pre-decoding signals into at least one column address group by decoding column addresses, outputs the pre-decoding signals for each group, and outputs a second pre-decoding signal group which is an inverted signal of a first pre-decoding signal group from among the plurality of pre-decoding signals. The column decoder outputs column selection signals by decoding the plurality of pre-decoding signals in a manner that operation of a metal oxide semiconductor (MOS) transistor is controlled by the first pre-decoding signal group and the second pre-decoding signal group.