Address Decoder for Non-Power-of-Two Memory Boundaries
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Solution Overview
Problem
Conventional memory sub-systems are limited by their ability to only support power-of-two addressable unit address boundaries, which restricts their performance in applications requiring non-power-of-two address boundaries, such as accessing data in non-uniform units across ranks or channels, leading to inefficiencies in concurrency and data access interleaving.
Innovation Solution
The implementation of an address decoder that supports non-power-of-two addressable unit address boundaries by using an interleaving factor and bit map to specify channel, rank, bank, row, and column addresses, allowing for flexible address mapping and improved data access efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional power-of-two address boundaries are used, then device complexity is reduced and ease of manufacture is improved, but adaptability and versatility are limited for non-power-of-two address requirements
Solution Approach 1:
The address decoder is designed to handle both power-of-two and non-power-of-two address boundaries through a unified decoding logic. The system uses a general-purpose address map configuration mechanism that can adapt to different address boundary requirements, making the decoder universal rather than specialized for only power-of-two boundaries.
Solution Approach 2:
The patent changes the addressing parameters by introducing configurable address maps that define custom address boundaries. Instead of being fixed to power-of-two boundaries, the system allows parameters such as channel width, rank size, and bank dimensions to be configured for non-power-of-two values, enabling flexible memory organization.
2Productivity
If non-power-of-two address boundaries are supported, then adaptability and data access efficiency are improved, but device complexity increases
Solution Approach 1:
The system performs preliminary address translation by configuring address maps in advance that define the mapping between linear addresses and physical memory locations. This pre-computed mapping table approach allows the address decoder to efficiently translate non-power-of-two addresses without complex runtime calculations, improving data access efficiency while managing complexity through upfront configuration.
Solution Approach 2:
The patent introduces an address map as an intermediary layer between the host interface and the physical memory array. This intermediate structure translates host-generated addresses into physical memory addresses, allowing the system to support non-power-of-two boundaries without requiring complex decoding logic throughout the entire memory subsystem. The address map acts as a mediator that simplifies the overall system complexity.
3Reliability
If fixed power-of-two address boundaries are used, then device complexity is minimized, but concurrency and data access interleaving performance deteriorate
Solution Approach 1:
The memory address space is segmented into hierarchical components (channels, ranks, banks, rows, columns) with configurable boundaries for each segment. This segmentation allows independent optimization of each memory component's size and boundaries, enabling non-power-of-two dimensions in specific segments while maintaining power-of-two in others, thus improving concurrency performance without requiring complete redesign of the entire addressing structure.
Data Source
AI summary
A system generating, using a first addressable unit address decoder, a first addressable unit address based on an input address, an interleaving factor, and a number of first addressable units. The system then generating, using an internal address decoder, an internal address based on the input address, the interleaving factor, and the number of first addressable units. Generating the internal address includes: determining a lower address value by extracting lower bits of the internal address, determining an upper address value by extracting upper bits of the internal address, and adding the lower address value to the upper address value to generate the internal address. Using an internal power-of-two address boundary decoder and the internal address, the system then generating a second addressable unit address, a third addressable unit address, a fourth addressable unit address, and a fifth addressable unit address.