Address Decoding Circuit with Dynamic Bank Enable Control

The patent implements dynamic bank enablement where banks can be selectively activated or deactivated based on address failure detection. The decoding circuit includes enable signals that dynamically control which banks are accessible, allowing the system to adapt its operational capacity in response to failures rather than statically reserving redundant addresses.

The patent changes the operational parameter of bank accessibility by introducing enable signals controlled by decoding units. When address failures are detected, the system modifies the enable state of specific banks, effectively changing which memory regions are accessible without altering the physical memory structure or capacity.

The patent divides the memory into multiple independent banks, each with its own decoding unit and enable control. This segmentation allows failures to be isolated to specific banks while other banks remain operational, enabling the system to handle multiple address failures simultaneously without affecting overall memory capacity.

The patent enables selective activation of banks based on failure patterns. When address failures occur in specific banks, those banks are disabled while other banks continue to operate at full capacity. This partial action approach maintains more functional memory than would be possible with traditional redundant address schemes.