Address Detection Circuit for Memory Word Line Disturbance
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Solution Overview
Problem
As the integration of memories increases, the reduced space between word lines in memory devices leads to a coupling effect known as word line disturbance, causing data degradation in adjacent memory cells due to frequent activation, especially during refresh operations.
Innovation Solution
An address detection circuit is implemented to minimize the number of addresses stored, detect frequently activated word lines, and refresh adjacent word lines to prevent data degradation, comprising address storage units, calculation units, a control unit, and a detection unit that counts and identifies addresses activated a reference number of times to trigger targeted refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of address storage units is increased to detect all frequently activated word lines, then the detection accuracy is improved, but the circuit area increases
Solution Approach 1:
The patent applies partial action by storing only a limited number of addresses (N addresses) in the address storage units rather than all possible addresses. The system detects frequently activated word lines among these N stored addresses, which is sufficient for practical purposes while significantly reducing the circuit area compared to storing all possible addresses.
Solution Approach 2:
The patent changes the parameter of address storage capacity from comprehensive (all possible addresses) to limited (N addresses). By adjusting this parameter, the system achieves a balance between detection accuracy for frequently activated word lines and circuit area reduction.
2Reliability
If all word lines are refreshed during refresh operations, then data integrity is maintained, but the refresh time increases
Solution Approach 1:
The patent applies local quality by differentiating the refresh treatment for different word lines. Instead of uniformly refreshing all word lines, the system identifies frequently activated word lines and their adjacent word lines as requiring special attention. The refresh control unit then performs targeted refresh operations on these specific word lines, maintaining data integrity where it matters most while reducing overall refresh time.
Solution Approach 2:
The address detection circuit performs preliminary detection during active operations to identify frequently activated word lines before the refresh operation. This preliminary action enables the refresh control unit to prepare and execute targeted refresh operations in advance, optimizing both data integrity and refresh time.
3Reliability
If adjacent word lines are refreshed to prevent word line disturbance, then data degradation is prevented, but the complexity of refresh control increases
Solution Approach 1:
The patent introduces an intermediary approach by using the address detection circuit as a mediator between the refresh control unit and the word lines. The address detection circuit analyzes active operations and provides information about frequently activated word lines to the refresh control unit, which then determines which adjacent word lines need refreshing. This intermediary structure simplifies the overall control logic by separating the detection and control functions.
Solution Approach 2:
The system implements feedback by continuously monitoring active operations through the address detection circuit, which detects frequently activated word lines and provides this information back to the refresh control unit. This feedback loop enables the refresh control unit to dynamically adjust refresh operations based on actual usage patterns, preventing data degradation while managing complexity through automated decision-making.
Data Source
AI summary
An address detection circuit comprises first to N-th address storage units suitable for storing an address, first to N-th calculation units each suitable for performing a counting operation when an address is stored in a corresponding address storage unit among the address storage units or the address stored in the corresponding address storage unit is inputted, a control unit suitable for sequentially storing an input address in the address storage units, and storing the input address in a selected address storage unit among the address storage units when of the address storage units each store an address, and a detection unit suitable for detecting an address, which is inputted a reference number of times or more, among the addresses stored in the address storage units, based on outputs of the calculation units.