Address-Differentiated DRAM Refresh for Retention Yield
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Solution Overview
Problem
Dynamic random access memories (DRAMs) face challenges in maintaining production yield due to decreasing cell retention times as process geometries shrink, leading to discarded devices and increased refresh rates, which compromise performance.
Innovation Solution
Implementing address-differentiated refresh rates by distinguishing between normal-retention and low-retention storage rows within DRAMs, where retention information is recorded and used to adjust refresh operations, allowing for salvaging devices that would otherwise be discarded by refreshing low-retention rows at a faster rate without increasing the overall refresh overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh rate is increased to maintain data retention in low-retention storage rows, then data reliability is improved, but refresh overhead increases and performance deteriorates
Solution Approach 1:
The patent applies address-differentiated refresh rates where low-retention storage rows receive a first refresh rate while normal-retention rows receive a second, lower refresh rate. This local differentiation allows targeted refresh operations only where needed, improving data retention reliability without unnecessarily increasing refresh overhead across the entire memory device, thus preserving overall performance.
2Productivity
If the refresh rate is increased to salvage low-retention devices, then production yield is improved, but refresh overhead increases
Solution Approach 1:
By implementing address-differentiated refresh rates, the patent enables selective refreshing of only those storage rows with low retention characteristics. This allows manufacturers to salvage devices that would otherwise be discarded, improving production yield, while the refresh overhead increase is localized and minimized rather than applied uniformly across all rows.
Solution Approach 2:
The patent segments storage rows into two categories: low-retention rows requiring faster refresh and normal-retention rows with standard refresh requirements. This segmentation is achieved through testing and classification processes that identify retention characteristics, enabling differentiated refresh strategies that improve yield without excessive overhead.
3Device complexity
If uniform refresh rate is applied to all storage rows, then device complexity is reduced, but low-retention rows fail to meet retention requirements
Solution Approach 1:
The patent implements address-differentiated refresh rates that apply different refresh frequencies to different storage row categories. Low-retention rows receive a first refresh rate while normal-retention rows receive a second refresh rate. This local quality approach maintains relatively simple device architecture while ensuring that each storage row type receives the appropriate refresh treatment to meet its retention requirements.
Data Source
AI summary
A method of testing a dynamic random access memory (DRAM) device that has N rows of storage cells and that requires, in at least one operating mode, at least N refresh commands to be received from an external source within a specified time interval. The rows of storage cells are tested in a first retention test to identify rows that fail to retain data over the specified time interval. The rows that fail to retain data over the specified time interval are tested in a second retention test to identify rows that retain data over an abbreviated time interval, the abbreviated time interval being shorter than the specified time interval.