Address Dispatcher for Fault Attack Detection in Memory Systems

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Solution Overview

Problem

Existing data handling systems face challenges in detecting fault attacks, particularly long fault attacks that span multiple reading operations across different memory regions, making it difficult to ensure the security and integrity of data.

Innovation Solution

A method involving an address dispatcher that sends multiple read requests to a memory region, with a redundant third read request to detect anomalies, and an anomaly signal producer that generates signals if results do not match, combined with a second read request to a different memory region outside the attack's influence to enhance detection of fault attacks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple read requests are sent to the same memory region with redundancy, then fault attack detection capability is improved, but reading operation time is increased

Engineering Contradiction:
Improvefault attack detection capabilityVSAvoidreading operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The system performs preliminary read requests before the actual data reading operation. By sending read requests to memory regions before the main reading operation, the system can detect fault attacks in advance and prevent them from affecting the main operation, thus improving detection capability without significantly impacting the main reading time

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system compares the results of redundant read requests with the main read request results. If discrepancies are detected, anomaly signals are generated and the reading operation is repeated or corrected. This feedback mechanism enables reliable fault detection while maintaining efficient reading operations through selective repetition

Inventive Principle:
Principle #23Feedback

2Reliability

If read requests are dispatched to multiple memory regions, then detection of long fault attacks is improved, but device complexity is increased

Engineering Contradiction:
Improvedetection of long fault attacksVSAvoidaddress dispatcher complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory access operation is segmented into multiple independent read requests to different memory regions. The address dispatcher divides the reading operation into separate requests that can be processed in parallel or sequence, allowing fault detection across multiple regions without requiring a completely complex system architecture

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The address dispatcher is designed to handle multiple types of read requests (normal reads, redundant reads, detection reads) using the same basic hardware structure. This multi-functional design allows the system to detect long fault attacks across multiple memory regions without adding separate dedicated detection hardware, thus reducing overall device complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Reliability

If redundant read requests are added to detect faults, then data integrity is improved, but processing speed is reduced

Engineering Contradiction:
Improvedata integrityVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system adds only the necessary redundant read requests to detect faults, not all possible reads. By sending a limited number of additional requests (excessive action) only when needed, the system improves data integrity without significantly impacting processing speed. The redundancy is partial and targeted rather than complete

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentEP3057027B1Method for secure data reading, computer program product and data handling system
Publication Date: 2018.06.13 NXP BV
  • EP3057027B1 patent drawingFigure 1
  • EP3057027B1 patent drawingFigure 2A
  • EP3057027B1 patent drawingFigure 2B

AI summary

There is disclosed a method for secure data reading in a data handling system, said data handling system comprising an address dispatcher for dispatching read requests to a memory comprising a first memory region, an anomaly signal producer and an anomaly handler, the method comprising the following steps: the address dispatcher dispatches a first read request to a first memory region; subsequent to dispatching the first read request, the address dispatcher dispatches a second read request to said first memory region; subsequent to dispatching the second read request, the address dispatcher dispatches a third read request to said first memory region; the anomaly signal producer produces a first anomaly signal if a result produced by the memory in response to the first read request does not agree with a result produced by the memory in response to the third read request; the anomaly signal producer produces a second anomaly signal if the memory does not produce a predefined result in response to the second read request; the anomaly handler concludes that a fault attack has occurred if at least one of the first anomaly signal and the second anomaly signal has been produced. Furthermore, a corresponding computer program product and a corresponding data handling system are disclosed.