Hardware Address-Event Network Simulation for Neural Processing
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Solution Overview
Problem
Neural network simulations, particularly spiking neural networks, are excessively slow on general-purpose computers due to high computational loads, making them inefficient for large-scale simulations.
Innovation Solution
A hardware-based address-event-representation network simulation system with interconnected processing modules that include source and target tables, state management logic, and learning logic to efficiently simulate and update node states and weights, allowing for rapid message exchange among nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If neural network simulation is performed on general-purpose computers, then the simulation can be executed with flexible programming, but the simulation speed is excessively slow due to high computational load
Solution Approach 1:
The patent replaces the mechanical computation system of general-purpose computers with a specialized hardware architecture designed specifically for neural network simulations. The hardware structure includes processing elements, weight memory, and interconnection networks that directly implement neural network operations in parallel, eliminating the sequential processing bottleneck of software-based simulations on general-purpose machines.
Solution Approach 2:
The patent changes the fundamental operational parameters by transitioning from software execution on von Neumann architecture to hardware implementation with parallel processing capabilities. The hardware structure uses dedicated circuits for weight storage, activation function computation, and spike propagation, enabling simultaneous processing of multiple neural operations that would otherwise require sequential execution.
2Quantity of substance
If the network size is increased to improve modeling capability, then the computational load increases proportionally, making simulation even slower
Solution Approach 1:
The patent divides the large-scale neural network into multiple independent processing elements that can operate simultaneously. Each processing element handles a subset of neurons and their connections, allowing the overall simulation to proceed in parallel. The hardware architecture includes multiple weight memory units and processing elements that can be configured to represent different portions of the network.
Solution Approach 2:
The patent introduces spatial parallelism by distributing neural network computations across multiple hardware components in three-dimensional space. Instead of processing neurons sequentially in time, the hardware architecture enables simultaneous processing across multiple processing elements, effectively adding a spatial dimension to the computation that scales with network size.
3Measurement precision
If training is performed on large numbers of input patterns to improve learning accuracy, then the required simulation time increases to weeks or months
Solution Approach 1:
The patent enables continuous training by maintaining the neural network simulation in a persistent hardware state rather than resetting between training iterations. The hardware structure allows spike trains to flow continuously through the network, with weight updates occurring in real-time based on learning rules, eliminating the need to restart simulations for each training pattern.
Solution Approach 2:
The patent pre-loads weight values into dedicated hardware memory structures before training begins, and maintains these weights in a ready-state throughout training. The hardware architecture includes pre-configured interconnection networks and activation function circuits that are prepared in advance, allowing immediate processing of training patterns without initialization delays.
Data Source
AI summary
A system, method, and design structure for address-event-representation network simulation are provided. The system includes a hardware structure with a plurality of interconnected processing modules configured to simulate a plurality of interconnected nodes. To simulate each node, the hardware structure includes a source table configured to receive an input message and identify a weight associated with a source of the input message. The hardware structure also includes state management logic configured to update a node state as a function of the identified weight, and generate an output signal responsive to the updated node state. The hardware structure further includes a target table configured to generate an output message in response to the output signal, identify a target to receive the output message, and transmit the output message. The hardware structure may further include learning logic configured to combine information about input messages and generated output signals, and to update weights.