Address Extension Circuit for Multi-State Pin Encoding
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Solution Overview
Problem
As the number of slave devices in a communication system increases, the number of address pins required for each chip also increases, leading to larger chip size and higher costs, necessitating an address extension circuit that can expand address configurations without adding more pins.
Innovation Solution
An address extension circuit that encodes chip addresses based on state information of existing address pins, including high/low levels, floating, and coupling with communication input/output pins, allowing one address pin to represent multiple states and configurations, thereby expanding address possibilities without increasing pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of address pins is increased to support more slave devices, then the address configuration capability is improved, but the chip size and cost increase
Solution Approach 1:
The patent changes the electrical state parameters of existing address pins to encode multiple address values. By utilizing different voltage levels (high/low), impedance states (floating/high impedance), and timing characteristics, the same physical pin can represent multiple address states, thereby increasing address configuration capability without adding more pins or increasing chip size
Solution Approach 2:
The patent makes existing address pins serve multiple functions by having them represent more than one address state. A single address pin can indicate multiple address values depending on its electrical state, making the pin universal for both traditional binary addressing and the extended multi-state addressing scheme, thus improving versatility without increasing device complexity
2Adaptability or versatility
If the number of address pins is increased to support more slave devices, then the address configuration capability is improved, but the cost increases
Solution Approach 1:
The patent utilizes parameter changes in electrical characteristics (voltage level, impedance state, timing) of existing pins to encode multiple address values, eliminating the need for additional address pins and the associated manufacturing costs of extra I/O structures, bond pads, and packaging pins
Solution Approach 2:
The patent creates virtual address extensions by encoding multiple address states in the electrical parameters of existing pins rather than creating physical copies of additional pins. This virtual multiplication of address capacity avoids the proportional increase in manufacturing cost that would result from adding physical pins
3Adaptability or versatility
If existing address pins are used to represent multiple states, then the address possibilities are expanded, but the difficulty of detecting and measuring address states increases
Solution Approach 1:
The patent implements feedback mechanisms where the master device samples the electrical states of address pins at specific timing intervals and uses this feedback to decode the multi-state address information. The system continuously monitors pin states during communication initialization to accurately determine which address value is being indicated, overcoming the detection difficulty through active sampling and decoding logic
Solution Approach 2:
The patent employs periodic sampling of address pin states during the communication setup phase. The master device periodically checks the electrical state of address pins at defined time intervals to capture the multi-state information, using this periodic measurement approach to reliably detect and measure the encoded address values despite the complexity of multiple states
Data Source
AI summary
An address extension circuit for configuring an address of a chip, can include where: the address extension circuit is configured to encode the address of the chip differently according to different state information of at least one address pin of the chip; and the state information of the address pin is configured to comprise at least one of floating, coupling with a communication input pin of the chip, and coupling with a communication output pin of the chip.