Address Fault Detection via ECC Parity Scrambling
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Solution Overview
Problem
Current memory devices face challenges in accurately detecting and correcting address faults, which can lead to data corruption and errors during read and write operations, especially at high data transfer speeds.
Innovation Solution
An address fault detection system that utilizes error correction code (ECC) parity bits to scramble and descramble data, detecting incorrect memory addresses by inverting ECC bits based on address parity, and raising flags for potential address faults, thereby minimizing data errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high-speed data transfer is implemented in memory devices, then productivity is improved, but reliability deteriorates due to increased susceptibility to address faults and data corruption
Solution Approach 1:
The patent applies preliminary action by generating and storing the address parity bit during the write operation before the actual data storage. This pre-computed parity information is then used during read operations to detect address faults, enabling early preparation of error detection mechanisms that work effectively at high data transfer speeds without adding detection latency.
2Reliability
If address fault detection is implemented, then reliability is improved, but device complexity increases due to additional parity generation and comparison circuitry
Solution Approach 1:
The patent applies universality by designing the ECC system to perform multiple functions: traditional data error correction and the new address fault detection. The same ECC circuitry that corrects data bit errors is also used to generate and verify address parity bits, allowing a single system to handle both error correction and address validation without requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent applies discarding and recovering by utilizing the existing ECC parity bit infrastructure and repurposing it for address fault detection. Instead of adding completely new detection mechanisms, the system recovers and reuses the computational resources already allocated for error correction, thereby detecting address faults while minimizing additional hardware complexity.
3Reliability
If additional storage is allocated for address fault detection, then reliability is improved, but manufacturing precision requirements increase due to tighter space constraints
Solution Approach 1:
The patent applies merging by combining the address parity bit storage with the existing ECC parity bit storage structures. The address parity information is integrated into the same memory locations and storage circuits that hold the traditional ECC data, eliminating the need for separate dedicated storage resources and reducing the overall space requirements for implementing address fault detection.
Solution Approach 2:
The patent applies universality by making the existing ECC storage infrastructure serve dual purposes: storing both data error correction information and address fault detection parity bits. This multi-functional use of storage resources avoids the need for additional storage allocation and maintains manufacturing feasibility by utilizing already-provisioned memory resources.
Data Source
AI summary
A memory device is provided. The memory device includes a memory bank configured to store data in one or more memory cells. The memory device further includes an address fault detection system designed to detect a mismatch between the address originally used to store the data and the address subsequently used to read the data. The address fault detection system generates an address parity bit from the received address and either stores that address parity bit with the user data or uses the address parity bit to invert the internal ECC bits generated from the user data. The address fault detection system can determine from the resulting syndrome from the ECC bits whether or not an address fault has occurred and raise an address fault indication flag if the address fault is detected.