Address Fault Detection in Memory via Segmented Parity Storage

Solution Overview

Problem

Conventional address fault detection systems in integrated circuits (ICs) experience delays and increased design complexity due to the generation of parity data based on both reference data and addresses during write and read operations, leading to inefficiencies and reliability issues.

Innovation Solution

An address fault detection system that writes reference data to one memory block and parity data to another, using a separate set of addresses, allowing for efficient detection of address faults without relying on address-based parity generation, thus reducing operational delays and design complexity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity data is generated based on both reference data and addresses during write and read operations, then address fault detection capability is improved, but operational delays and design complexity increase

Engineering Contradiction:

Improveaddress fault detection capabilityVSAvoiddesign complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory into separate first and second memory blocks, with the first block storing reference data and the second block storing parity data. This segmentation allows independent storage and retrieval of parity information, eliminating the need for complex address-based parity generation during operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary action by pre-storing parity data in the second memory block during fabrication or initialization. This eliminates the need for real-time parity calculation during read/write operations, reducing operational delays while maintaining detection capability.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If parity data is generated based on both reference data and addresses during write and read operations, then address fault detection capability is improved, but operational delays increase

Engineering Contradiction:

Improveaddress fault detection capabilityVSAvoidoperational delays

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by pre-storing parity data in the second memory block during fabrication or initialization. This eliminates the need for real-time parity calculation during read/write operations, reducing operational delays while maintaining detection capability.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses a copy of the reference data (stored as parity data in the second memory block) to enable fault detection without requiring real-time computation. The parity data serves as a pre-computed copy that can be directly compared during operations.

Inventive Principle:

Principle #26Copying

3Reliability

If parity data is generated based on both reference data and addresses during write and read operations, then address fault detection capability is improved, but design complexity increases

Engineering Contradiction:

Improveaddress fault detection capabilityVSAvoiddesign complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the memory into separate first and second memory blocks, with the first block storing reference data and the second block storing parity data. This segmentation allows independent storage and retrieval of parity information, eliminating the need for complex address-based parity generation during operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces an intermediary approach by using a separate memory block to store parity data, which acts as a mediator between the reference data and the fault detection process. This intermediary storage eliminates the need for complex real-time computation.

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS11853157B2Address fault detection system

Publication Date: 2023.12.26 NXP BV

AI summary

An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.