Address-Based Data Forwarding Circuit for Shared Bus Routing
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Solution Overview
Problem
Existing circuit designs require an excessive number of conductive lines to communicate with other circuits, leading to increased size requirements and signal interference.
Innovation Solution
The implementation of a data-distributing circuit that reduces the number of conductive lines by using a receiving circuit to receive data from a source circuit and a forwarding circuit to deliver it to the appropriate circuit based on a target address, utilizing fewer conductive lines for communication between a source circuit and multiple recipient circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple conductive lines are used to connect source circuit to multiple recipient circuits, then communication capability is improved, but circuit area and signal interference increase
Solution Approach 1:
The patent merges multiple data transmission paths into a single shared conductive line by implementing a data bus structure where multiple recipient circuits share common data lines (D0-D7). The source circuit can communicate with multiple recipients through this shared bus, eliminating the need for separate dedicated lines for each recipient and significantly reducing the total number of conductive lines required.
Solution Approach 2:
The conductive lines in the patent serve multiple functions and multiple circuits simultaneously. The same data bus lines (D0-D7) are used by the source circuit to communicate with multiple different recipient circuits (C0-C7), making the communication infrastructure universal rather than dedicated. This multi-functionality allows one set of lines to replace what would otherwise require multiple separate line sets.
2Adaptability or versatility
If multiple conductive lines are used to connect source circuit to multiple recipient circuits, then communication capability is improved, but signal interference increases
Solution Approach 1:
By merging communication paths into a shared bus structure, the patent reduces the total number of conductive lines in the circuit. Fewer lines mean reduced electromagnetic interference between adjacent lines, as there are simply fewer sources of interference. The shared bus approach consolidates what would be multiple separate transmission paths into a single controlled environment.
Solution Approach 2:
The patent introduces address decoding logic and control circuits as intermediaries that manage communication on the shared bus. These intermediary components enable selective communication between the source and specific recipients by decoding address signals and enabling/disabling data transmission to particular circuits. This mediation allows multiple circuits to share the same physical lines without constant interference, as only the intended recipient is active during each transmission.
3Reliability
If dedicated conductive lines are used for each circuit communication, then communication reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple dedicated communication channels into a single shared bus system. Instead of having separate dedicated lines for each source-recipient pair, the system uses one shared data bus that all circuits access. This merging reduces the complexity of routing and connecting numerous dedicated lines while maintaining communication reliability through controlled access mechanisms and address-based selection.
Solution Approach 2:
The shared conductive lines serve multiple circuits and multiple communication purposes simultaneously. The same data bus lines (D0-D7) are universally used by the source circuit to communicate with any of the recipient circuits (C0-C7), eliminating the need for dedicated lines for each connection. This universal infrastructure reduces device complexity while maintaining the ability to reliably communicate with any recipient through address-based selection.
Data Source
AI summary
A circuitry includes a source circuit; a first circuit; a second circuit; and a data-distributing circuit including: a receiving circuit configured to receive a first datum for the first circuit via a first and second front line, and to receive from the source circuit a second datum for the second circuit via a third front line and a fourth front line; and a forwarding circuit configured to receive one of the first datum and the second datum via a first intermediate line and a second intermediate line, to receive a target address associated with the one of the first datum and the second datum via a third intermediate line, and, according to the target address, provide the one of the first datum and the second datum to one of the first circuit and the second circuit.