Address Generation Circuit for Semiconductor Memory Timing Control
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Solution Overview
Problem
Semiconductor memory devices face delays in column address control during data input/output operations due to the need for additional delay cells to compensate for timing issues, leading to increased current consumption and chip size, especially at high data rates.
Innovation Solution
An address generation circuit with a first and second address control clock generation unit, an address counting unit, and a repair control unit that generates redundancy addresses by comparing initial counting addresses with repair addresses, optimizing column address control through clock signal management and latch operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional delay cells are used to compensate for timing delay in column address control, then timing synchronization is improved, but current consumption increases
Solution Approach 1:
The patent applies preliminary action by generating the second address control clock signal in advance during an initial period before the main data input/output operation. This allows the address control to be synchronized without requiring additional delay cells during high-speed operation, thereby reducing current consumption while maintaining timing reliability.
2Reliability
If additional delay cells are used to compensate for timing delay in column address control, then timing synchronization is improved, but chip size increases
Solution Approach 1:
The patent eliminates the need for physical delay cells by performing address control synchronization in advance through the second address control clock signal. This preliminary action approach reduces the chip area by removing the requirement for additional delay cell circuits while maintaining proper timing synchronization.
3Reliability
If additional delay cells are used to compensate for timing delay in column address control, then timing synchronization is improved, but process voltage temperature variations increase
Solution Approach 1:
The patent performs address control synchronization in advance using the second address control clock signal before the main operation begins. This preliminary synchronization is less sensitive to PVT variations compared to delay cells operating during high-speed data input/output, thereby improving adaptability to process, voltage, and temperature conditions.
4Reliability
If column address repair operation is performed to replace failure memory cells, then manufacturing reliability is improved, but data input/output speed decreases
Solution Approach 1:
The patent performs the column address repair operation in advance during the initial period when the second address control clock signal is generated. By completing the repair operation before the main data input/output operation begins, the patent enables high-speed data transfer without being constrained by the slower repair process, thus maintaining both manufacturing reliability and data transfer speed.
Data Source
AI summary
An address generation circuit includes: a first address control clock generation unit suitable for generating a first address control clock signal in response to an internal clock signal; a second address control clock generation unit suitable for generating a second address control clock signal in response to one of an address initialization signal and the first address control clock signal; an address counting unit suitable for counting the second address control clock signal and generating a counting address; and a repair control unit suitable for latching the counting address in response to the second address control clock signal, comparing the latched counting address with a repair address, and generating a redundancy address based on the comparison result.