Address Generation Circuit Latch Segmentation for Memory Refresh
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Solution Overview
Problem
In memory devices, frequent activation and precharging of word lines can lead to data loss due to changes in electric charges stored in capacitors, and electromagnetic interference can further damage memory cell data during refresh operations, necessitating periodic recharging and redundancy operations to maintain data integrity.
Innovation Solution
An address generation circuit with a reduced number of latches is implemented, including first, second, and third latch units, along with an addition/subtraction unit, to generate and maintain addresses during target refresh operations, ensuring accurate addressing and data retention by controlling word lines and redundancy word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent word line activation and precharging is performed to maintain data, then data retention is improved, but data damage occurs due to electromagnetic interference and charge changes in adjacent memory cells
Solution Approach 1:
The patent segments the address generation into multiple latch units (first latch unit for inverted address, second latch unit for added/subtracted address, third latch unit for maintenance) to selectively control which addresses are generated during different refresh scenarios, preventing electromagnetic interference while maintaining data retention
Solution Approach 2:
The patent dynamically switches between different address generation paths based on operation type: using the first latch unit for normal refresh, second latch unit for target refresh with addition/subtraction, and third latch unit for maintenance, adapting the address generation mechanism to the specific operational context
2Measurement precision
If multiple latch units are used to generate accurate addresses for refresh operations, then addressing precision is improved, but circuit complexity increases
Solution Approach 1:
The patent implements multi-functional latch units that serve different purposes: the first latch unit handles address inversion, the second latch unit performs addition/subtraction for target refresh, and the third latch unit maintains addresses, with each unit being selectively activated based on the refresh operation type to achieve precise addressing while managing circuit complexity
Solution Approach 2:
The patent prepares multiple latch units in advance with different address generation capabilities, so that when a refresh operation is needed, the appropriate pre-configured latch unit can be immediately activated without complex runtime decision logic, reducing operational complexity while maintaining precision
Data Source
AI summary
An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.