Address Generation Unit for Multi-Dimensional Data Access
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Solution Overview
Problem
Current electronic devices lack a unified architecture or platform that can efficiently perform multiple data processing tasks such as modulation, demodulation, encryption, decryption, encoding, decoding, and transcoding for various applications like video, audio, and telecommunications simultaneously, requiring complex hardware and software integration.
Innovation Solution
A data processing architecture that includes an address generation unit using end point patterns to calculate real addresses for accessing multi-dimensional data structures, allowing for flexible and simultaneous performance of various tasks without the need for supporting hardware, utilizing a vector processor unit (VPU) array and a crossbar switch for scalable interconnectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple data processing tasks are performed simultaneously using traditional hardware components, then processing capability is improved, but device complexity increases significantly
Solution Approach 1:
The patent implements a unified data processing architecture where a single platform can perform multiple tasks including modulation, demodulation, encryption, decryption, encoding, decoding, and transcoding. The system uses a general-purpose processor with programmable function blocks that can be configured for different processing tasks, eliminating the need for separate dedicated hardware components for each function.
Solution Approach 2:
The patent combines multiple data processing functions into a single integrated platform. Instead of using separate hardware chips for modulation, encryption, video processing, and other functions, the invention merges these capabilities into one system that can execute all tasks through software programming of function blocks.
2Productivity
If specialized hardware components are used for each data processing function, then processing efficiency is improved, but hardware requirements and integration complexity increase
Solution Approach 1:
The patent replaces dedicated hardware components with a software-based processing model. Instead of having separate physical chips for each function, the system uses a general-purpose processor with programmable function blocks that can be configured through software to perform any data processing task, substituting mechanical hardware specialization with software flexibility.
Solution Approach 2:
The system employs a universal processing platform where a single set of hardware resources can be programmed to perform multiple different data processing functions. The function blocks can be reconfigured through software to handle different algorithms and processing requirements without requiring physical hardware changes.
3Device complexity
If a unified platform is implemented to perform multiple data processing tasks, then device complexity is reduced, but processing capability for simultaneous tasks may be compromised
Solution Approach 1:
The patent divides the data processing functionality into separate function blocks that can be independently programmed and executed. Each function block handles a specific processing task, and multiple blocks can operate simultaneously on different data streams. This segmentation allows the unified platform to maintain high processing capability while reducing hardware integration complexity.
Solution Approach 2:
The system uses dynamically reconfigurable function blocks that can be programmed at runtime to perform different operations. The processing architecture is flexible and adaptive, allowing the same hardware platform to be reconfigured for different processing requirements without physical changes, thus maintaining high productivity while simplifying hardware design.
Data Source
AI summary
A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.