Address Generator Circuit for Single-Buffer Array Transposition
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Solution Overview
Problem
Existing methods for transposing two-dimensional arrays in integrated circuits require two memory banks, which consume a large amount of memory and are limited to arrays with rows and columns that are powers of two, making it desirable to use single-buffering for arrays with different dimensions to reduce cost and latency.
Innovation Solution
An address generator circuit with a status flag generation circuit, modulo adder circuit, and address processing circuit is used to generate read and write access signals for a single storage circuit, allowing the transposition of two-dimensional arrays with arbitrary row and column counts by employing modulo arithmetic and delayed signals to efficiently map input to output positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If two memory banks are used for transposing two-dimensional arrays, then read and write operations can be performed simultaneously, but memory consumption and device complexity increase
Solution Approach 1:
The patent employs periodic action by alternating between write and read phases in a single memory bank. During write phase, data is stored in the memory bank; during read phase, the transposed data is retrieved. This periodic switching allows the system to achieve transposition functionality without requiring simultaneous read-write capability, thus eliminating the need for a second memory bank while maintaining transposition speed
Solution Approach 2:
The patent merges the functions of two separate memory banks into a single memory bank by carefully coordinating address generation and timing. The address generator circuit produces write addresses and read addresses that sequentially access the same memory bank, combining the storage and retrieval functions that previously required separate physical memory banks, thereby reducing memory consumption and device complexity
2Productivity
If two memory banks are used for transposing two-dimensional arrays, then simultaneous read and write operations are enabled, but device complexity increases
Solution Approach 1:
The patent merges the functions of two separate memory banks into a single memory bank by carefully coordinating address generation and timing. The address generator circuit produces write addresses and read addresses that sequentially access the same memory bank, combining the storage and retrieval functions that previously required separate physical memory banks, thereby reducing memory consumption and device complexity
Solution Approach 2:
The single memory bank is designed to serve multiple functions: it acts as both the write buffer and read buffer at different time phases. The same physical memory bank is universally used for both storing input data and retrieving transposed output data, eliminating the need for dedicated separate memory banks and reducing overall device complexity
3Quantity of substance
If single-buffering is used for transposing two-dimensional arrays, then memory consumption and device complexity are reduced, but latency increases
Solution Approach 1:
The patent employs periodic action by alternating between write and read phases in a single memory bank. During write phase, data is stored in the memory bank; during read phase, the transposed data is retrieved. This periodic switching allows the system to achieve transposition functionality without requiring simultaneous read-write capability, thus eliminating the need for a second memory bank while maintaining transposition speed
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing address sequences in lookup tables before the actual transposition operation. The address generator circuit uses these pre-computed addresses to efficiently navigate the memory bank during write and read phases, reducing the computational overhead and latency during the actual transposition process
4Adaptability or versatility
If traditional address generation methods are used, then arrays with rows and columns as powers of two are supported, but adaptability to arbitrary dimensions is limited
Solution Approach 1:
The patent applies parameter changes by using variable address increment values that adapt to the specific dimensions of the input array. The address generator circuit modifies its addressing parameters (row stride, column stride, increment values) based on the actual array dimensions provided, allowing it to handle arbitrary dimensions rather than being restricted to power-of-two sizes. This dynamic parameter adjustment enables versatility while managing complexity through systematic address calculation
Data Source
AI summary
The present embodiments relate to an address generator circuit for addressing a storage circuit. The address generator circuit may generate address signals for read and write access operations at the storage circuit. The write access operation may store a two-dimensional array in the storage circuit and the read access operation may retrieve a transpose of the two-dimensional array from the storage circuit. The address generator circuit may include a status flag generation circuit that generates status flag signals, a modulo adder circuit that receives first and second signals and computes a modulo adder output signal, and an address processing circuit. The address processing circuit may receive the modulo adder output signal from the modulo adder circuit and the plurality of status flag signals from the status flag generation circuit and provide the first and second signals to the modulo adder circuit.