Address Generator for Parallel Image Frame Processing
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Solution Overview
Problem
Current image processing systems face challenges in efficiently processing multiple image frames or windows in parallel, particularly in driver assistance applications, due to the need for different gain/exposure settings and the use of color filters, which can reduce sensor resolution and intensity response, limiting the simultaneous use of image frames for various applications.
Innovation Solution
An image processing system with a vector processor and an address generator that calculates addresses over multiple image frames or windows, allowing for parallel processing using a single hardware platform, where the address generator is programmed with parameters for an execution loop and can generate a break signal to halt looping code, enabling efficient processing of multiple driver assistance applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If color filters are used in the image sensor, then color information can be captured, but sensor resolution and intensity response are reduced
Solution Approach 1:
The image sensor is divided into two distinct sensor arrays: a first image sensor without color filters for high-resolution grayscale imaging, and a second image sensor with color filters for color information capture. This segmentation allows each sensor to specialize in one function, maintaining high resolution where needed while capturing color where required.
Solution Approach 2:
A processor acts as an intermediary between the two sensor arrays, receiving data from both sensors and combining the grayscale information from the first sensor with color information from the second sensor to produce a composite color image. This mediator integrates the strengths of both sensing approaches.
2Reliability
If multiple image frames are processed sequentially, then processing accuracy can be maintained, but processing speed and productivity are reduced
Solution Approach 1:
The system performs preliminary actions by capturing multiple image frames simultaneously using multiple sensors rather than sequentially processing single frames. This parallel capture approach maintains accuracy through multiple measurements while significantly improving processing speed by eliminating sequential bottlenecks.
Solution Approach 2:
Multiple image frames from different sensors are merged into a composite data structure that combines grayscale and color information. This merging allows the system to process enriched image data at higher speeds by leveraging parallel sensor operation rather than sequential frame processing.
3Device complexity
If a single hardware platform is used for multiple driver assistance applications, then device complexity is reduced, but computation units may be occupied by address calculation tasks
Solution Approach 1:
The address calculation function is extracted from the general-purpose computation units and implemented as a dedicated address generator component. This extraction frees up the computation units to focus entirely on image processing tasks while the specialized address generator handles memory addressing efficiently.
Solution Approach 2:
An address generator acts as an intermediary between the computation units and memory, handling all address calculation tasks for multiple image frames. This mediator protects the computation units from being occupied by address arithmetic, allowing them to maintain high productivity on image processing operations.
Data Source
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AI summary
An image processing system including a vector processor and a memory adapted for attaching to the vector processor. The memory is adapted to store multiple image frames. The vector processor includes an address generator operatively attached to the memory to access the memory. The address generator is adapted for calculating addresses of the memory over the multiple image frames. The addresses may be calculated over the image frames based upon an image parameter. The image parameter may specify which of the image frames are processed simultaneously. A scalar processor may be attached to the vector processor. The scalar processor provides the image parameter(s) to the address generator for address calculation over the multiple image frames. An input register may be attached to the vector processor. The input register may be adapted to receive a very long instruction word (VLIW) instruction. The VLIW instruction may be configured to transfer only: (i) parameters for image processing calculations over the image frames by the ALU units and (ii) a single bit to the address generator.