Address Generator for Multi-MAC FFT Computing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional multi-MAC techniques require a controller to call instructions from program memory every clock cycle, leading to increased load and reduced efficiency in systems using multiple multiply-accumulate (MAC) circuits for applications like FFT computations.
Innovation Solution
A multi-functional computing apparatus and FFT computing apparatus that utilize a controller-independent address generator with a lookup table or state machine to generate read/write addresses, allowing the memory to deliver data groups to MAC/multiply circuits without continuous controller intervention, thereby reducing the controller's burden and minimizing memory capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a controller calls instructions from program memory every clock cycle for multi-MAC operations, then the system can execute multiple multiply-accumulate operations in parallel, but the controller load increases and system efficiency decreases
Solution Approach 1:
The address generator is designed to autonomously generate read and write addresses for memory operations without requiring controller intervention. The address generator uses internal counters and logic to automatically produce sequential and patterned address sequences, allowing the system to serve itself and reducing the controller's instructional burden while maintaining parallel MAC operations
Solution Approach 2:
The system divides the control function into two independent parts: the controller handles high-level operation coordination while the address generator handles low-level address sequencing. This segmentation allows the address generation task to be performed independently by dedicated hardware, reducing the controller load and enabling efficient parallel MAC operations
2Speed
If multiple MAC circuits are used for parallel operations, then computation speed increases, but memory capacity requirements increase
Solution Approach 1:
The address generator implements periodic address generation patterns that efficiently reuse memory locations across different MAC operations. By generating addresses in systematic periodic sequences, the same memory banks can be reused for multiple MAC stages, reducing the total memory capacity needed while supporting parallel computation
Solution Approach 2:
The patent introduces a time dimension to memory access by using banks with different access patterns and timing. Multiple MAC circuits can simultaneously access different memory banks or the same banks at different time cycles, effectively increasing computational throughput without proportionally increasing total memory capacity
Data Source
AI summary
Provided is a multi-functional computing apparatus including a multiply-accumulate (MAC) unit having a plurality of MAC circuits, an address generator configured to generate a read address group having a plurality of read addresses, and a memory having a plurality of banks for storing a plurality of read data groups, wherein the address generator delivers the generated read address group to the memory, and the memory delivers a read data group corresponding to the read address group selected from among the plurality of read data groups, the read data group including a plurality of pieces of read data.