Address History Caches for Consistent Out-of-Order Packet Transfer
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Solution Overview
Problem
Existing computing systems face inefficiencies in data transfer due to limited bandwidth at fabric boundaries and data transfer inefficiencies between processing nodes, particularly when connecting separate dies or processing nodes, which is exacerbated by the use of fewer physical wires.
Innovation Solution
Implementing a packet transmitter and receiver system with request queues, address history caches, and queue arbiters that compress packet data by storing only the address identifier instead of the full address, allowing for more efficient data transfer by using compressed packets and adjusting packet formats to avoid data corruption during out-of-order processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transferred through fabric boundaries between separate dies or processing nodes, then communication between processing units is enabled, but bandwidth is reduced due to fewer physical wires available at boundaries
Solution Approach 1:
The address is segmented into two parts: an address space identifier (first portion) and an offset (second portion). Only the offset is transmitted in the packet, while the address space identifier is retrieved from a cache on the receiving end. This segmentation reduces packet size and increases data transfer efficiency across fabric boundaries with limited physical wires.
Solution Approach 2:
The address space identifier is pre-stored in a cache memory on the receiving processing node before the actual data transfer occurs. When a packet arrives with an offset, the receiver can quickly reconstruct the full address by combining the cached identifier with the received offset, eliminating the need to transmit the entire address and improving bandwidth utilization.
2Productivity
If packet size is reduced by storing only address identifiers, then bandwidth utilization improves, but data corruption risk increases during out-of-order processing
Solution Approach 1:
Sequence numbers are assigned to packets in advance before transmission. The receiving end uses these pre-assigned sequence numbers to detect out-of-order arrivals and implement corrective actions such as discarding out-of-order packets or adjusting the address space identifier cache, thereby maintaining data integrity while using compressed packet formats.
Solution Approach 2:
The system implements feedback mechanisms where the receiver monitors packet arrival order using sequence numbers and provides control signals back to the transmitter or adjusts its own cache state. When out-of-order packets are detected, the system can invalidate or update the address space identifier cache appropriately, ensuring that compressed packets are correctly mapped to their destination addresses without corruption.
Data Source
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AI summary
Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple fabric interfaces in clients and a fabric. A packet transmitter in the fabric interface includes multiple queues, each for storing packets of a respective type, and a corresponding address history cache for each queue. Queue arbiters in the packet transmitter select candidate packets for issue and determine when address history caches on both sides of the link store the upper portion of the address. The packet transmitter sends a source identifier and a pointer for the request in the packet on the link, rather than the entire request address, which reduces the size of the packet. The queue arbiters support out-of-order issue from the queues. The queue arbiters detect conflicts with out-of-order issue and adjust the outbound packets and fields stored in the queue entries to avoid data corruption.